This paper presents a novel technique to realize Karnin et al.'s (k,n)-threshold schemes over binary field extensions as a software. Our realization uses the matrix representation of finite fields and matrix-vector multiplications, and enables rapid operations in software implementation. The theoretical evaluation and computer simulation reveal that our realization of Karnin et al.'s scheme achieves much faster processing time than the ordinary symbol oriented realization of the scheme. Further, we show that our realization has comparable performance to the existing exclusive-OR-based fast schemes of Fujii et al. and Kurihara et al.

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

Fair exchange is an important tool to achieve “fairness” of electronic commerce. Several previous schemes satisfy universally composable security which provides security preserving property under complex networks like the Internet. In recent years, as the demand for electronic commerce increases, fair exchange for electronic vouchers (e.g., electronic tickets, moneys, etc.) to obtain services or contents is in the spotlight. The definition of fairness for electronic vouchers is different from that for general electronic items (e.g., the sender must not do duplicate use of exchanged electronic vouchers). However, although there are universally composable schemes for electronic items, there is no previous study for electronic vouchers. In this paper, we introduce a universally composable definition of fair voucher exchange, that is, an ideal functionality of fair voucher exchange. Also, we prove the equivalence between our universally composable definition and the conventional definition for electronic vouchers. Thus, our formulation of the ideal functionality is justified. Finally, we propose a new fair voucher exchange scheme from non-blocking atomic commitment as black-box, which satisfies our security definition and is adequate for mobile environments. By instantiating general building blocks with known practical ones, our scheme can be also practical because it is implemented without trusted third party in usual executions.

Brain-Computer Interfaces (BCIs) are systems that translate one's thoughts into commands to restore control and communication to severely paralyzed people, and they are also appealing to healthy people. One of the challenges is to improve the performance of BCIs, often measured by the accuracy and the trial duration, or the information transfer rate (ITR), i.e., the mutual information per unit time. Since BCIs are communications between a user and a system, error control schemes such as forward error correction and automatic repeat request (ARQ) can be applied to BCIs to improve the accuracy. This paper presents reliability-based ARQ (RB-ARQ), a variation of ARQ designed for BCIs, which employs the maximum posterior probability for the repeat decision. The current results show that RB-ARQ is more effective than the conventional methods, i.e., better accuracy when trial duration was the same, and shorter trial duration when the accuracy was the same. This resulted in a greater information transfer rate and a greater utility, which is a more practical performance measure in the P300 speller task. The results also show that such users who achieve a poor accuracy for some reason can benefit the most from RB-ARQ, which could make BCIs more universal.

If a d-dimensional pure simplicial complex C has a shelling, which is a specific total order of all facets of C, C is said to be shellable. We consider the problem of deciding whether C is shellable or not. This problem is solved in linear time of m, the number of all facets of C, if d = 1 or C is a pseudomanifold in d = 2. Otherwise it is unknown at this point whether the decision of shellability can be solved in polynomial time of m. Thus, for the latter case, we had no choice but to apply a brute force method to the decision problem; namely checking up to the m! ways to see if one can arrange all the m facets of C into a shelling. In this paper, we introduce a new concept, called h-assignment, to C and propose a practical method using h-assignments to decide whether C is shellable or not. Our method can make the decision of shellability of C by smaller sized computation than the brute force method.

When a link or node fails in a network, the affected flows are automatically rerouted. This increases the hop counts of the flows, which can drastically degrade network performance. Keeping the hop lengths as stable as possible, i.e., minimizing the difference in hop length between the original flow and the rerouted flow is important for network reliability. Therefore, network service providers need a method for designing networks that stabilizes the flow hop length and maintains connectivity during a link or node failure with limited investment cost. First, we formulate the network design problem used for determining the set of links to be added that satisfies the required constraints on flow hop length stability, connectivity, and node degree. Next, we prove that this problem is NP-complete and present two approximation algorithms for the optimization problem so as to minimize the number of links added. Evaluation of the performance of these algorithms by using 39 backbone networks of commercial ISPs and networks generated by two well-known models showed that the proposed algorithms provide effective solutions in sufficiently short computation time.

In optical packet switches, the overhead of reconfiguring a switch fabric is not negligible with respect to the packet transmission time and can adversely affect switch performance. The overhead increases the average waiting time of packets and worsens throughput performance. Therefore, scheduling packets requires additional considerations on the reconfiguration frequency. This work intends to analytically find the optimal reconfiguration frequency that minimizes the average waiting time of packets. It proposes an analytical model to facilitate our analysis on reconfiguration optimization for input-buffered optical packet switches with the reconfiguration overhead. The analytical model is based on a Markovian analysis and is used to study the effects of various network parameters on the average waiting time of packets. Of particular interest is the derivation of closed-form equations that quantify the effects of the reconfiguration frequency on the average waiting time of packets. Quantitative examples are given to show that properly balancing the reconfiguration frequency can significantly reduce the average waiting time of packets. In the case of heavy traffic, the basic round-robin scheduling scheme with the optimal reconfiguration frequency can achieve as much as 30% reduction in the average waiting time of packets, when compared with the basic round-robin scheduling scheme with a fixed reconfiguration frequency.

Recent Location Based Services (LBS) extend not only information services such as car navigation services, but supporting various applications such as augmented reality and emergency services in ubiquitous computing environments. However location based services in the ubiquitous computing environment bring several security issues such as location privacy and forgery. While the privacy of the location based service is considered as the important security issue, security against location forgery is less considered. In this paper, we propose improved Han et al.'s protocol [1] that provides more lightweight computation. Our proposed model also improves the credibility of LBS by deploying multiple location sensing technologies.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

This paper presents a simplifying method of the two previous fault attacks to pairing and the Miller algorithms based on a practical fault assumption. Our experimental result shows that the assumption is feasible and easy to implement.

We present a design optimization method of H-plane waveguide components, based on the level set method with the finite element method. In this paper, we propose a new formulation for the improvement of a level set function, which describes shape, location, and connectivity of dielectric in a design region. Employing the optimization procedure, we demonstrate that optimized structures of an H-plane waveguide filter and T-junction are obtained from an initial structure composed of several circular blocks of dielectric.

A fifth-order switched-capacitor (SC) complex filter was implemented in 0.2-µm CMOS technology. A novel SC integrator was developed to reduce the die size and current consumption of the filter. The filter is centered at 24.730.15 kHz (3δ) and has a bandwidth of 20.260.3 kHz (3δ). The image channel is attenuated by more than 42.6 dB. The in-band third-order harmonic input intercept point (IIP3) is 17.3 dBm, and the input referred RMS noise is 34.3 µVrms. The complex filter consumes 350 µA with a 2.0-V power supply. The die size is 0.578 mm2. Owing to the new SC integrator, the filter achieves a 27% reduction in die size without any degradation in its characteristics, including its noise performance, compared with the conventional equivalent.

Motion blur in TFT-LCD is caused by sample and hold characteristic, slow response time of liquid crystal, and the inconsistency between object tracking of the human eye and the actual object location. In order to solve this problem, a high frame rate driving method based on motion estimation and motion compensation has been applied to LCD products. However, as the required processing time of motion estimation increases in LCD TV and monitor systems, real-time video image processing becomes more difficult. Frame interpolation through the large macro block (MB) size has limitations to detect small objects. So, this paper proposes the efficient motion estimator architecture which uses seven kinds of macro blocks to enhance the accuracy of motion estimation and combines the parallel processing with pre-computation technology and hardware optimization for high-speed processing. Also, for increased efficiency in the hardware architecture, we employed an I2C (Inter Integrated Circuit) communication unit to control the key parameters easily through the personnel computer. Simulation results show that the critical path at the motion estimator is reduced by about 27.47% compared to the conventional structure. As a result, the proposed motion estimator will be applicable for the high-speed frame interpolation of variable video.

In this paper, a 24 GHz frequency source for low phase noise is presented in a 0.18 µm CMOS process. The 24 GHz frequency source chip is composed of a 12 GHz voltage controlled oscillator (VCO) and a 24 GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12 GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17 dBc/Hz at a 1 MHz offset frequency and -20.95 dB at 23.19 GHz frequency, respectively. The measured frequency tuning range is from 23.19 GHz to 24.76 GHz drawing 2.72 mA at a supply voltage of 1.8 V not including an output buffer.

Let p be an odd prime number. We define a family of quaternary sequences of period 2p using generalized cyclotomic classes over the residue class ring modulo 2p. We compute exact values of the linear complexity, which are larger than half of the period. Such sequences are 'good' enough from the viewpoint of linear complexity.

Automatic recognition of finger gestures can be used for promotion of life quality. For example, a senior citizen can control the home appliance, call for help in emergency, or even communicate with others through simple finger gestures. Here, we focus on one-stroke finger gesture, which are intuitive to be remembered and performed. In this paper, we proposed and evaluated an accelerometer-based method for detecting the predefined one-stroke finger gestures from the data collected using a MEMS 3D accelerometer worn on the index finger. As alternative to the optoelectronic, sonic and ultrasonic approaches, the accelerometer-based method is featured as self-contained, cost-effective, and can be used in noisy or private space. A compact wireless sensing mote integrated with the accelerometer, called MagicRing, is developed to be worn on the finger for real data collection. A general definition on one-stroke gesture is given out, and 12 kinds of one-stroke finger gestures are selected from human daily activities. A set of features is extracted among the candidate feature set including both traditional features like standard deviation, energy, entropy, and frequency of acceleration and a new type of feature called relative feature. Both subject-independent and subject-dependent experiment methods were evaluated on three kinds of representative classifiers. In the subject-independent experiment among 20 subjects, the decision tree classifier shows the best performance recognizing the finger gestures with an average accuracy rate for 86.92 %. In the subject-dependent experiment, the nearest neighbor classifier got the highest accuracy rate for 97.55 %.

In this paper, we present a new frequency identification technique using the recent methodology of compressive sensing and discrete prolate spheroidal sequences with optimal energy concentration. Using the bandpass form of discrete prolate spheroidal sequences as basis matrix in compressive sensing, compressive frequency sensing algorithm is presented. Simulation results are given to present the effectiveness of the proposed technique for application to detection of carrier-frequency type signal and recognition of wideband signal in communication.

In this paper, we propose a novel coding scheme for the geometry of the triangular mesh model. The geometry coding schemes can be classified into two groups: schemes with perfect reconstruction property that maintains their connectivity, and schemes without it in which the remeshing procedure is performed to change the mesh to semi-regular or regular mesh. The former schemes have good coding performance at higher coding rate, while the latter give excellent coding performance at lower coding rate. We propose a geometry coding scheme that maintains the connectivity and has a perfect reconstruction property. We apply a method that successively structures on 2-D plane the surrounding vertices obtained by expanding vertex sequences neighboring the previous layer. Non-separable component decomposition is applied, in which 2-D structured data are decomposed into four components depending on whether their location was even or odd on the horizontal and vertical axes in the 2-D plane. And a prediction and update are performed for the decomposed components. In the prediction process the predicted value is obtained from the vertices, which were not processed, neighboring the target vertex in the 3-D space. And the zero-tree coding is introduced in order to remove the redundancies between the coefficients at similar positions in different resolution levels. SFQ (Space-Frequency Quantization) is applied, which gives the optimal combination of coefficient pruning for the descendant coefficients of each tree element and a uniform quantization for each coefficient. Experiments applying the proposed method to several polygon meshes of different resolutions show that the proposed method gives a better coding performance at lower bit rate when compared to the conventional schemes.

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 µW at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ in the temperature range from 0 to 100 and 12.8 ppm/ from 30 to 100. The current TC is 119.2 ppm/ at temperatures of 0 to 100. Measurement results also demonstrate a stable voltage reference at high temperature (> 30), and a constant current reference at low temperature (< 70).