Energy harvesting has been widely investigated as a potential solution to supply power for Internet of Things (IoT) devices. Computing devices must operate intermittently rather than continuously, because harvested energy is unstable and some of IoT applications can be periodic. Therefore, processors for IoT devices with intermittent operation must feature a hibernation mode with zero-standby-power in addition to energy-efficient normal mode. In this paper, we describe the layout design and measurement results of a nonvolatile standard cell memory (NV-SCM) and nonvolatile flip-flops (NV-FF) with a nonvolatile memory using Fishbone-in-Cage Capacitor (FiCC) suitable for IoT processors with intermittent operations. They can be fabricated in any conventional CMOS process without any additional mask. NV-SCM and NV-FF are fabricated in a 180nm CMOS process technology. The area overhead by nonvolatility of a bit cell are 74% in NV-SCM and 29% in NV-FF, respectively. We confirmed full functionality of the NV-SCM and NV-FF. The nonvolatile system using proposed NV-SCM and NV-FF can reduce the energy consumption by 24.3% compared to the volatile system when hibernation/normal operation time ratio is 500 as shown in the simulation.

In conventional video streaming systems, various kind of video streams are delivered from a dedicated server (e.g., edge server) to the subscribers so that a video stream of higher quality level is encoded with a higher bitrate. In this paper, we consider the problem of delivering those video streams with the assistance of Peer-to-Peer (P2P) technology with as small server cost as possible while keeping the performance of video streaming in terms of the throughput and the latency. The basic idea of the proposed method is to divide a given video stream into several sub-streams called stripes as evenly as possible and to deliver those stripes to the subscribers through different tree-structured overlays. Such a stripe-based approach could average the load of peers, and could effectively resolve the overloading of the overlay for high quality video streams. The performance of the proposed method is evaluated numerically. The result of evaluations indicates that the proposed method significantly reduces the server cost necessary to guarantee a designated delivery hops, compared with a naive tree-based scheme.

Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.

We prepared a bR thin film by the wire-bar coating technique, and investigated the transient photo-current characteristics of the bR photocell. The transient photo-current signal of bR photocells prepared by the wire-bar coating technique and the dip coating technique was compared. An almost identical transient photo-current signal intensity was obtained both for the wire-bar coating technique and dip coating technique, while the thickness of bR thin film prepared by the wire-bar coating technique is slightly thinner than that prepared by the dip-coating technique. Transparent conductive oxide dependence of the transient photo-current signal is almost the same dependence for the bR photocells with a bR thin film prepared by both techniques. Application of the wire-bar coating technique is significant from the viewpoints of the bR's sample consumption as well as simplicity of sample preparation.

The coarse-grained reconfigurable architecture (CGRA) is a promising computing platform that provides both high performance and high power-efficiency. The computation-intensive portions of an application (e.g. loop nests) are often mapped onto CGRA for acceleration. However, mapping loop nests onto CGRA efficiently is quite a challenge due to the special characteristics of CGRA. To optimize the mapping of loop nests onto CGRA, this paper makes three contributions: i) Establishing a precise performance model of mapping loop nests onto CGRA, ii) Formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, iii) Extracting an efficient heuristic algorithm and building a complete flow of mapping loop nests onto CGRA (PolyMAP). Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 27% on average, as compared to the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

We propose the asynchronous receiver-initiated MAC protocol with the stair-like sleep mode; each node reduces its own sleep time by the sleep-change-rate depending on the number of hops from the source to the sink in wireless sensor networks (WSNs). Using the stair-like sleep approach, our protocol achieves high delivery ratio, low packet delay, and high energy efficiency due to the reduction in idle listening time. Our protocol can formulate the upper bound of the idle listening time because of the feature that the sleep time decreases in a geometric progression, and the reduction of the idle listening time is obtained by using the stair-like sleep approach. In our proposed scheme, the sink calculates the sleep change rate based on the number of hops from the source to the sink. By using the control packets which have the role of the acknowledgment (ACK), our proposed protocol can achieve the stair-like sleep with no additional control packets. In addition, even in the network condition that multi-targets are detected, and the number of hops to the sink are changed frequently, our proposed protocol can change the sleep change rate adaptively because the sink can always obtain the number of hops from the source to the sink. Simulation results show that the proposed protocol can improve the performance in terms of the packet delivery ratio, the packet delay, and the energy efficiency compared to the conventional receiver-initiated MAC (RI-MAC) protocol.

This paper proposes a method for reconstructing a smooth and accurate 3D surface. Recent machine vision techniques can reconstruct accurate 3D points and normals of an object. The reconstructed point cloud is used for generating its 3D surface by surface reconstruction. The more accurate the point cloud, the more correct the surface becomes. For improving the surface, how to integrate the advantages of existing techniques for point reconstruction is proposed. Specifically, robust and dense reconstruction with Shape-from-Silhouettes (SfS) and accurate stereo reconstruction are integrated. Unlike gradual shape shrinking by space carving, our method obtains 3D points by SfS and stereo independently and accepts the correct points reconstructed. Experimental results show the improvement by our method.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

A hybrid buffer structured optical packet switch and its scheduling algorithm are presented for a limited number of tunable wavelength convertors (TWCs) and internal wavelengths. The hybrid buffer consists of the fiber delay line (FDL) buffer and the electronic buffer. With the proposed algorithm, it could lead realizable packet loss reduction that the LAUC-VF algorithm with only the FDL buffer does not reach. Also, we optimized the number of TWCs and internal wavelengths of the hybrid buffer structured OPS. For the fully shared TWC structure, the optimum number of TWCs and internal wavelengths to guarantee minimum packet loss is evaluated to prevent resource waste under the hybrid buffer.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Transient routing loops have been observed to form in Mobile Ad-hoc Networks running the OLSRv2 proactive link-state routing protocol. The packets falling into loops impact the surrounding network thus degrading throughput even though only a small proportion of the traffic may enter these loops and only for a short time. This becomes significantly more evident when Link Layer Notification is used to catch broken links, inadvertently leading to an increase in the number of loops. Two methods of Loop Detection are introduced and are used to trigger either Loop Suppression by selectively and preemptively discarding the looping packets that are unlikely to reach their destination, or Loop Correction by the notification of the routing protocol to cut the link over which the packet is looping. The newly introduced Loop Suppression and Loop Correction techniques used with Link Layer Notification are shown to significantly increase network performance over plain OLSRv2 and OLSRv2 with Link Layer Notification.

A Policy-based Network Management (PBNM) in Mobile Ad-hoc Networks (MANETs) should be efficient and reliable. In this letter, we propose a mechanism for the policy-based management in ad hoc networks and we discuss methods to discover the Policy Decision Point (PDP), set the management area, and manage the movements of nodes in the PBNM system. Finally, we assess the results through simulations.

When a store sells items to customers, the store wishes to determine the prices of the items to maximize its profit. Intuitively, if the store sells the items with low (resp. high) prices, the customers buy more (resp. less) items, which provides less profit to the store. So it would be hard for the store to decide the prices of items. Assume that the store has a set V of n items and there is a set E of m customers who wish to buy those items, and also assume that each item i ∈ V has the production cost di and each customer ej ∈ E has the valuation vj on the bundle ej ⊆ V of items. When the store sells an item i ∈ V at the price ri, the profit for the item i is pi=ri-di. The goal of the store is to decide the price of each item to maximize its total profit. We refer to this maximization problem as the item pricing problem. In most of the previous works, the item pricing problem was considered under the assumption that pi ≥ 0 for each i ∈ V, however, Balcan, et al. [In Proc. of WINE, LNCS 4858, 2007] introduced the notion of "loss-leader," and showed that the seller can get more total profit in the case that pi < 0 is allowed than in the case that pi < 0 is not allowed. In this paper, we derive approximation preserving reductions among several item pricing problems and show that all of them have algorithms with good approximation ratio.

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

Shared-Memory Optical Packet (SMOP) switch architecture is very promising for significantly reducing the amount of required optical memory, which is typically constructed from fiber delay lines (FDLs). The current reservation-based scheduling algorithms for SMOP switches can effectively utilize the FDLs and achieve a low packet loss rate by simply reserving the departure time for each arrival packet. It is notable, however, that such a simple scheduling scheme may introduce a significant packet out of order problem. In this paper, we first identify the two main sources of packet out of order problem in the current reservation-based SMOP switches. We then show that by introducing a "last-timestamp" variable and modifying the corresponding FDLs arrangement as well as the scheduling process in the current reservation-based SMOP switches, it is possible to keep packets in-sequence while still maintaining a similar delay and packet loss performance as the previous design. Finally, we further extend our work to support the variable-length burst switching.

A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.900.89 mm2.

During software requirements analysis, developers and stakeholders have many alternatives of requirements to be achieved and should make decisions to select an alternative out of them. There are two significant points to be considered for supporting these decision making processes in requirements analysis; 1) dependencies among alternatives and 2) evaluation based on multi-criteria and their trade-off. This paper proposes the technique to address the above two issues by using an extended version of goal-oriented analysis. In goal-oriented analysis, elicited goals and their dependencies are represented with an AND-OR acyclic directed graph. We use this technique to model the dependencies of the alternatives. Furthermore we associate attribute values and their propagation rules with nodes and edges in a goal graph in order to evaluate the alternatives with them. The attributes and their calculation rules greatly depend on the characteristics of a development project. Thus, in our approach, we select and use the attributes and their rules that can be appropriate for the project. TOPSIS method is adopted to show alternatives and their resulting attribute values.

In optical burst switching (OBS) networks, burst with different numbers of hops experience unfairness in terms of the burst loss probability. In this paper, we propose a preemptive scheme based on the number of transit hops in OBS networks. In our proposed scheme, preemption is performed with two thresholds; one is for the total number of hops of a burst and the other is for the number of transit hops the burst has passed through. We evaluate the performance of the scheme by simulation, and numerical examples show that the proposed scheme improves the fairness among the bursts with different numbers of hops, keeping the overall burst loss probability the same as that for the conventional OBS transmission without preemption.