Pedestrian detection from visual images, which is used for driver assistance or video surveillance, is a recent challenging problem. Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection and achieves the highest detection accuracy. However, its calculation cost is too large to calculate it in real-time on state-of-the-art processors. In this paper, to obtain optimal parallel implementation for an NVIDIA GPU, several kinds of parallelism of CoHOG-based detection are shown and evaluated suitability for implementation. The experimental result shows that the detection process can be performed at 16.5 fps in QVGA images on NVIDIA Tesla C1060 by optimized parallel implementation. By our evaluation, it is shown that the optimal strategy of parallel implementation for an NVIDIA GPU is different from that of FPGA. We discuss about the reason and show the advantages of each device. To show the scalability and portability of GPU implementation, the same object code is executed on other NVIDA GPUs. The experimental result shows that GTX570 can perform the CoHOG-based pedestiran detection 21.3 fps in QVGA images.

Nowadays, pedestrian recognition for automotive and security applications that require accurate recognition in images taken from distant observation points is a recent challenging problem in the field of computer vision. To achieve accurate recognition, both detection and tracking must be precise. For detection, some excellent schemes suitable for pedestrian recognition from distant observation points are proposed, however, no tracking schemes can achieve sufficient performance. To construct an accurate tracking scheme suitable for pedestrian recognition from distant observation points, we propose a novel pedestrian tracking scheme using multiple cues: HSV histograms and HOG features. Experimental results show that the proposed scheme can properly track a target pedestrian where tracking schemes using only a single cue fails. Moreover, we implement the proposed scheme on NVIDIA® TeslaTM C1060 processor, one of the latest GPU, to achieve real-time processing of the proposed scheme. Experimental results show that computation time required for tracking of a frame by our implementation is reduced to 8.80 ms even though Intel® CoreTM i7 CPU 975 @ 3.33 GHz spends 111 ms.

Dielectric rod arrays in a metallic waveguide alter the propagation modes and group velocities of electromagnetic waves. We have focused on TE30-to-TE10 mode converters and investigated how their behavior varies with frequency. A mode converter is proposed that passes the TE10 mode at frequencies lower than 2fc, and converts the TE30 mode into the TE10 mode for frequencies higher than 3fc.

In time division multiple access (TDMA)-based wireless mesh networks, interference relationships should be considered when time slots are assigned to links. In graph theory-based time slot assignment algorithms, the protocol interference model is widely used to determine radio interference information, although it is an inaccurate model of actual radio interference. On the other hand, the signal-to-interference-plus-noise-ratio model (SINR model) gives more accurate interference relationships but is difficult to apply to time slot assignment algorithms since the radio interference information cannot be determined before time slot assignment. In this paper, we investigate the effect of the parameters of the protocol interference model on the accuracy of the interference relationships determined using this model. Specifically, after assigning time slots to links based on the protocol interference model with various interference ratios, which is the major parameter of the protocol interference model, we compare the interference relationship among links in the protocol interference and SINR models. Through simulation experiments, we show that accuracy of the protocol interference model is improved by up to 15% by adjusting the interference ratios of the protocol interference model.

In this paper, a geometric source separation system using nonnegative matrix factorization (NMF) is proposed. The adaptive beamformer is the best method for geometric source separation, but it suffers from a “target signal cancellation” problem in multi-path situations. We modified the HALS-NMF algorithm for decomposition into bases, and developed an interference suppression module in order to cancel the interference bases. A performance comparison between the proposed and subband GSC-RLS algorithm using a MATLAB® simulation was executed; the results show that the proposed system is robust in multi-path situations.

Let (X,Y) be a Rd R-valued random vector. In regression analysis one wants to estimate the regression function m(x):=E(Y|X=x) from a data set. In this paper we consider the convergence rate of the error for the k nearest neighbor estimators in case that m is (p,C)-smooth. It is known that the minimax rate is unachievable by any k nearest neighbor estimator for p > 1.5 and d=1. We generalize this result to any d ≥ 1. Throughout this paper, we assume that the data is independent and identically distributed and as an error criterion we use the expected L2 error.

This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.

A perfect array is an array for which the autocorrelation function is impulsive. A parameterization of perfect arrays of real numbers is presented. Perfect arrays are represented by trigonometric functions. Three formulae are obtained according to the parities of the size of the array. Examples corresponding to each formula are shown. In the case of 66 arrays, the existence of a set of perfect arrays having integer components is shown.

We proposed a novel UV curable reactive mesogen monomer for VA-LCD with Polymer-Sustained (Stabilized) Vertical Alignment (PSVA) which shows a high display performance. The experimental results reveal that the PSVA by the novel-monomer realizes less image sticking and better response time.

In this paper, we evaluate the downlink performance of Transparent mode (T-mode) and Non-Transparent mode (NT-mode) in a two-hop cellular system based on IEEE 802.16j. In particular, we evaluate the performance in terms of the system capacity, optimal resource allocation, and outage probability using Monte Carlo simulation with various system parameters such as different Frequency Reuse Factors (FRFs) and the distance between Base Station (BS) and Relay Station (RS). To analyze the Signal to Interference and Noise Ratio (SINR) of the access and relay links, an SINR model is introduced for cellular multihop systems considering intra- and inter-cell interferences. Then, we present a method of optimal resource allocation for the Access Zone (AZ) and Relay Zone (RZ) to maximize the system capacity. Consequently, the simulation results provide an insight into choosing the appropriate RS position and optimal resource allocation. Through numerical examples, it is found that the FRFs of two and three are good choices to achieve the highest capacity with low outage in T- and NT-modes, respectively.

A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1 V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 µW and 0.126 mm2, respectively. The FoM is 47 fJ/conversion-step.

In this paper, we propose a two dimensional (2D) non-separable adaptive directional lifting (ADL) structure for discrete wavelet transform (DWT) and its image coding application. Although a 2D non-separable lifting structure of 9/7 DWT has been proposed by interchanging some lifting, we generalize a polyphase representation of 2D non-separable lifting structure of DWT. Furthermore, by introducing the adaptive directional filteringingto the generalized structure, the 2D non-separable ADL structure is realized and applied into image coding. Our proposed method is simpler than the 1D ADL, and can select the different transforming direction with 1D ADL. Through the simulations, the proposed method is shown to be efficient for the lossy and lossless image coding performance.

A new direction of arrival (DOA) estimation method is introduced with arbitrary array geometry when uncorrelated and coherent signals coexist. The DOAs of uncorrelated signals are first estimated via subspace-based high resolution DOA estimation technique. Then a matrix that only contains the information of coherent signals can be formulated by eliminating the contribution of uncorrelated signals. Finally a subspace block sparse reconstruction approach is taken for DOA estimations of the coherent signals.

In research community of content distribution, a new communication paradigm of rendezvous-based abstraction which easily enables location-free content-oriented services, attracts great attention. ID/Locator separation architecture is originally proposed for resolving increase of routing table size in the current Internet but it has possibility of supporting this abstraction because host ID is clearly separated from its location. This feature of ID/Locator separation means an end host can be identified by ID independent of its network layer protocol. So, ID/Locator separation architecture enables communication with end host(s) operating different network-layer protocol, which might increase candidate paths between host pairs and improve content distribution path. In this paper, we evaluate this improvement of shortest path brought by inter-layer 3 networking. In inter-layer 3 networking, a shared node connecting different network layer plane plays an important role. We evaluate shortest path improvement with various shared node locations and show that strategic assignment of shared nodes brings large improvement. When multiple layer 3 networks are available for users, shortest path might be improved even only with multi-homing (without inter-layer 3 networking). We also evaluate shortest path improvement brought by multi-homing and inter-layer 3 networking for incremental deployment scenario of multi-homing. Our simulation results show that inter-layer 3 networking brings great improvement even with small number of users deploying multi-homing while only multi-homing itself brings small improvement.

We propose a robust and efficient algorithm called ROCKET for clustering large-scale transaction databases. ROCKET is a divisive hierarchical algorithm that makes the most of recent hardware architecture. ROCKET handles the cases with the small and the large number of similar transaction pairs separately and efficiently. Through experiments, we show that ROCKET achieves high-quality clustering with a dramatic performance improvement.

Adaptive network coded cooperation (ANCC) scheme may have excellent performance for data transmission from a large collection of terminals to a common destination in wireless networks. However, the random relay selection strategy for ANCC protocol may generate the distributed low-density parity-check (LDPC) codes with many short cycles which may cause error floor and performance degradation. In this paper, an optimized relay selection strategy for ANCC is proposed. Before data communication, by exploiting low-cost information interaction between the destination and terminals, the proposed method generates good assembles of distributed LDPC codes and its storage requirement reduces dramatically. Simulation results demonstrate that the proposed relay selection protocol significantly outperforms the random relay selection strategy.

Short-range multiple-input and multiple-output (SR-MIMO) has attracted much attention, because the technique makes it possible to raise channel capacity to several hundred Gbit/s by utilizing the millimeter-wave band (e.g., 60 GHz band). Although the opposed transceiving antennas are assumed to be accurately positioned in previous studies regarding SR-MIMO, a very important issue is to evaluate the performance degradation due to displacement between MIMO transceivers. In SR-MIMO over the millimeter-wave band, any displacement is perceived as significant because the wavelength is small. This paper evaluates the influence on SR-MIMO transmission performance over millimeter-wave caused by displacement between the transmitting and receiving antennas. The channel capacity is found to degrade by 5% when the horizontal displacement is 1 mm and by 2.7% when the rotational displacement is 10 degrees. In addition, comparing performances obtained with a number of antenna array arrangements clarifies that a square pattern arrangement is suitable for short-range wireless transmission.

This paper presents novel hybrid push-pull protocols for peer-to-peer video streaming. Our approaches intend to reap the best of push- and pull-based schemes by adaptively switching back and forth between the two modes according to video chunk distributions. The efficacy of the proposed protocols is validated through an evaluation study that demonstrates substantial performance gains.

This paper presents a software-based parallel cryptographic solution with a massive-parallel memory-embedded SIMD matrix (MTX) for data-storage systems. MTX can have up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. Furthermore, a next-generation SIMD matrix called MX-2 has been developed by expanding processing-element capability of MTX from 2-bit to 4-bit processing. These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. Moreover, we have proposed combining Content Addressable Memory (CAM) technology with the massive-parallel memory-embedded SIMD matrix architecture to enable fast pipelined table-lookup coding. Since both arithmetic logical operation and table-lookup coding execute extremely fast on these architectures, efficient execution of encryption and decryption algorithms can be realized. Evaluation results of the CAM-less and CAM-enhanced massive-parallel SIMD matrix processor for the example of the Advanced Encryption Standard (AES), which is a widely-used cryptographic algorithm, show that a throughput of up to 2.19 Gbps becomes possible. This means that several standard data-storage transfer specifications, such as SD, CF (Compact Flash), USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) can be covered. Consequently, the massive-parallel SIMD matrix architecture is very suitable for private information protection in several data-storage media. A further advantage of the software based solution is the flexible update possibility of the implemented-cryptographic algorithm to a safer future algorithm. The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation and small Si-area consumption.

Generally, the failure rate of a sealed relay is regarded as a constant value, no matter where and how it is used. However, the failure processes of sealed relays won't be the same under different conditions, even for one relay, its failure rate also will be changed during operations. This paper studies the failure process of a kind of sealed relay by analyzing the variations of its time parameters. Among contact resistance and all those time parameters, it is found that closing gap time can indicate the failure process of tested relay very well. For the purpose of verifying this conclusion derived from time parameters, the contacts are observed by microscope after the tested relay failed. Both theoretical calculation result of contacts gap and photos taken by microscope show that the hypothetic failure mode derived from time parameters is reasonable. Based on the failure analysis, the paper also proposes a dynamic reliability estimation method with closing gap time.