Adaptable workflow participant assignment (WPA) is crucial to the efficiency and quality of workflow execution. This paper proposes an ontology-based approach to adaptable WPA (OWPA). OWPA introduces domain ontology to organize the enterprise data and uses a well-defined OWPA rule to express an authorization constraint. OWPA can represent more complex authorization constraints by flexibly using the enterprise data, the workflow data, the user-input data, and the built-in functions. By a high-usability interactive interface, OWPA allows users to define and modify the OWPA rules easily without any programming work. Moreover, OWPA is bound to the workflow modeling tool and the workflow monitor respectively to adapt to dynamic workflow modification in workflow definitions and workflow instances. OWPA has been applied in three enterprises in China.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

A novel analysis model for post-wall waveguide T-junctions is proposed. Equivalent solid-walls for the post-walls to have equal guided wavelength are corrected in the analysis model so that the wall thickness for the coupling windows is set to the difference in the width between the post-wall and the solid-wall waveguides. The accuracy of the proposed model is confirmed by comparing it to an HFSS analysis for the real structure of the post-wall waveguide T-junction including the post surfaces. 61.25 GHz model antennas are fabricated for experimental verification. The reflection of the antenna designed by the modified analysis model is suppressed to below -15 dB over a 5.6 GHz bandwidth, while that in the antenna designed by the conventional model is larger than -15 dB around the design frequency.

In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.

In this paper, a Stochastic Collocation Algorithm combined with Sparse Grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR) which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs Homogeneous Chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or Wavelet Bases to model the steady-state behavior in time domain. Secondly, contrary to Stochastic Galerkin Algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from Efficient Collocation Method, the heuristic approach which may result in "Rank deficient problem" and "Runge phenomenon," Sparse Grid technique is developed to select the collocation points needed in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied to any other kind of nonlinear system simulation with process variations, such as transient analysis, etc.

We propose an incremental relaying protocol in conjunction with partial relay selection with the aim of making efficient use of the degrees of freedom of the channels as well as improving the performance of dual hop relaying with partial relay selection (DRPRS). Specifically, whenever the direct link from the source to the destination is not favorable to decoding, the destination will request the help of the opportunistic relay providing highest SNR of the links from the source. Theoretical analyses, as well as simulation results, verify that our scheme outperforms the DRPRS scheme in terms of bit error probability.

The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (Fmin, Rn, Γ opt) of 45 nm node MOSFETs from 5 to 15 GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziel's model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100 nm. We confirmed that Pucel's noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50 nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.

We try to use a computer algebra system Mathematica as a test case generation system. In test case generation, we generally need to solve equations and inequalities. The main reason why we take Mathematica is because it has a built-in function to solve equations and inequalities. In this paper, we deal with both black-box testing and white-box testing. First, we show two black-box test case generation procedures described in Mathematica. The first one is based on equivalence partitioning. Mathematica explicitly shows a case that test cases do no exist. This is an advantage in using Mathematica. The second procedure is a modification of the first one adopting boundary value analysis. For implementation of boundary value analysis, we give a formalization for it. Next, we show a white-box test case generation procedure. For this purpose, we also give a model for source programs. It is like a control flow graph model. The proposed procedure analyzes a model description of a program.

Owing to their ultra-wideband characteristics, tapered slot antennas (TSAs) are used as element antennas in wideband phased arrays. However, when the size of a TSA is reduced in order to prevent the generation of a grating lobe during wide-angle beam scanning, the original ultra-wideband characteristics are degraded because of increased reflections from the ends of the tapered slot aperture. To overcome this difficulty, we propose a new antenna structure in which parallel-plate waveguides are added to the TSA. The advantage of this new structure is that the reflection characteristics of individual antenna elements are not degraded even if the width of the antenna aperture is very small, i.e., approximately one-half the wavelength of the highest operating frequency. In this study, we propose a procedure for designing the new antenna through numerical simulations by using the FDTD method. In addition, we verify the performance of the antenna array by experiments.

The proportionate normalized least mean square algorithm (PNLMS) greatly improves the convergence of the sparse impulse response. It exploits the shape of the impulse response to decide the proportionate step gain for each coefficient. This is not always suitable. Actually, the proportionate step gain should be determined according to the difference between the current estimate of the coefficient and its optimal value. Based on this idea, an approach is proposed to determine the proportionate step gain. The proposed approach can improve the convergence of proportionate adaptive algorithms after a fast initial period. It even behaves well for the non-sparse impulse response. Simulations verify the effectiveness of the proposed approach.

A physical random number generator, which generates truly random number trains by using the randomness of physical phenomena, is widely used in the field of cryptographic applications. We have developed an ultra high-speed superconductive physical random number generator that can generate random numbers at a frequency of more than 10 GHz by utilizing the high-speed operation and high-sensitivity of superconductive integrated circuits. In this study, we have statistically evaluated the quality of the random number trains generated by the superconductive physical random number generator. The performances of the statistical tests were based on a test method provided by National Institute of Standards and Technology (NIST). These statistical tests comprised several fundamental tests that were performed to evaluate the random number trains for their utilization in practical cryptographic applications. We have generated 230 random number trains consisting of 20,000-bits by using the superconductive physical random number generator fabricated by the SRL 2.5 kA/cm2 Nb standard process. The generated random number trains passed all the fundamental statistical tests. This result indicates that the superconductive random number generator can be sufficiently utilized in practical applications.

This letter presents an approach to the construction of multiple-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes based on hyperplanes (µ-flats) of two different dimensions in Euclidean geometries. The codes constructed with this method have the same code length, multiple-rate and large stopping sets while maintaining the same basic hardware architecture. The code performance is investigated in terms of the bit error rate (BER) and compared with those of the LDPC codes which are proposed in IEEE 802.16e standard. Simulation results show that our codes perform very well and have low error floors over the AWGN channel.

The aim of this work is to develop an efficient medical image segmentation technique by fitting a nonlinear shape model with pre-segmented images. In this technique, the kernel principle component analysis (KPCA) is used to capture the shape variations and to build the nonlinear shape model. The pre-segmentation is carried out by classifying the image pixels according to the high level texture features extracted using the over-complete wavelet packet decomposition. Additionally, the model fitting is completed using the particle swarm optimization technique (PSO) to adapt the model parameters. The proposed technique is fully automated, is talented to deal with complex shape variations, can efficiently optimize the model to fit the new cases, and is robust to noise and occlusion. In this paper, we demonstrate the proposed technique by implementing it to the liver segmentation from computed tomography (CT) scans and the obtained results are very hopeful.

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

We have developed an odor-emitting apparatus for application of odor to information technology. This apparatus consists of a chemical capsule cartridge including chemical capsules of odor ingredients and valves to control odor emission using an artificial metal muscle. In this method, multiple valves can be opened using the current for a single artificial muscle because the expansion and contraction time constant for the artificial muscles is large. We have developed a new multi-valve sequence mode that uses multiple odor capsules to increase odor strength, and we have been able to increase the strength produced by a factor of two. In addition, we evaluated the change in odor strength using a mock-up of the back seat of an automobile, and all of the ten test subjects reported sensing a stronger odor.

A continuous belief propagation (BP) decoding algorithm for a hybrid automatic repeat request (ARQ) system is proposed in this paper. The proposed continuous BP decoding algorithm utilizes the extrinsic information generated in the last iteration of the previous transmission for a continuous progression of the decoding through retransmissions. This allows the continuous BP decoding algorithm to accelerate the decoding convergence for codeword determination, especially when the number of retransmissions is large or a currently combined packet has punctured nodes. Simulation results verify the effectiveness of the proposed continuous BP decoding algorithm.

Fast Fourier Transform (FFT) is an important algorithm in many digital signal processing applications, and it often requires parallel implementation for high throughput. In this paper, we first present the SmartCell coarse-grained reconfigurable architecture targeted for stream processing. A SmartCell prototype integrates 64 processing elements, configurable interconnections, and dedicated instruction and data memories into a single chip, which is able to provide high performance parallel processing while maintaining post-fabrication flexibility. Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. This algorithm provides an optimized data flow pattern that reduces both communication and configuration overheads. The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device. Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and MorphoSys implementations, respectively. SmartCell also achieves the energy efficiency gains of 2.1 and 28.9 when compared with FPGA and DSP implementations.

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

Various observation models have been introduced into the object tracking community, and combining them has become a promising direction. This paper proposes a novel approach for estimating the confidences of different observation models, and then effectively combining them in the particle filter framework. In our approach, spatial Likelihood distribution is represented by three simple but efficient parameters, reflecting the overall similarity, distribution sharpness and degree of multi peak. The balance of these three aspects leads to good estimation of confidences, which helps maintain the advantages of each observation model and further increases robustness to partial occlusion. Experiments on challenging video sequences demonstrate the effectiveness of our approach.