This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.

A low-loss ultra-wide band (UWB) filter is presented, which uses miniaturized parallel coupled line along with an standard printed circuit board (PCB) technology. By analyzing even- and odd-mode impedances (in comparison with conventional parallel coupled lines) of miniaturized parallel coupled line, this structure provides tight coupling, thus, relaxing the requirements on physical dimensions width and spacing when designing broadband filters. A bandpass filter for Mode 1 (the first 3 sub-bands) in the 3.1-5 GHz band for Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB is realized and compared with a conventional parallel coupled line filter. The experimental results show as much as 0.9 dB insertion loss improvement over the conventional counterpart.

A novel circularly polarized antenna with square slot for broadband characteristics is proposed in this paper. The horizontal and vertical components of the L-shaped probe, which is a key element to generate circular polarization, are separated in the structure, contrary to the concept of joined probes. Another novelty, placing stubs in the slot, which are attached to the ground plane, is proposed to improve the axial ratio (AR) characteristics of the antenna by around 10%. Placing a reflector at a distance of λ0/4 from the antenna to obtain unidirectional patterns is effective when no stubs are placed in the slot. The antenna attains a < 10 dB return loss bandwidth of 47.5% (2.76-4.48 GHz) and < 3 dB axial ratio (AR) bandwidth of 42.47% (2.67-4.11 GHz) in measurement. Parametric studies on key parameters and measured results are also presented.

Dicode partial response signaling system over inductively-coupled channel has been developed to achieve higher data rate than self-resonant frequencies of inductors. The developed system operates at five times higher data rates than conventional systems with the same inductor. A current-mode equalization in the transmitter designed in a 90-nm CMOS successfully reshapes waveforms to obtain dicode signals at the receiver. For a 5-Gb/s signaling through the coupled inductors with a 120-µm diameter and a 120-µm distance, 20-mV eye opening was observed. The power consumption value of the transmitter was 58 mW at the 5-Gb/s operation.

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100 k-gate blocks, which is 7.1 X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

There are a great amount of various resources described in many different ways for service oriented grid environment, while traditional grid resource discovery methods could not fit more complex future grid system. Therefore, this paper proposes a novel grid resource discovery method based on association rule hypergraph partitioning algorithm which analyzes user behavior in history transaction records to provide personality service for user. And this resource discovery method gives a new way to improve resource retrieval and management in grid research.

We describe a parameter estimation method for a target object in an area that sensors monitor. The parameters to be estimated are the perimeter length, size, and parameter determined by the interior angles of the target object. The estimation method does not use sensor location information, only the binary information on whether each sensor detects the target object. First, the sensing area of each sensor is assumed to be line-segment-shaped, which is a model of an infrared distance measurement sensor. Second, based on the analytical results of assuming line-segment-shaped sensing areas, we developed a unified equation that works with general sensing areas and general target-object shapes to estimate the parameters of the target objects. Numerical examples using computer simulation show that our method yields accurate results.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

One typical phonotactic system for language recognition is parallel phone recognition followed by vector space modeling (PPRVSM). In this system, various phone recognizers are applied in parallel and fused at the score level. Each phone recognizer is trained for a known language, which is assumed to extract complementary information for effective fusion. But this method is limited by the large amount of training samples for which word or phone level transcription is required. Also, score fusion is not the optimal method as fusion at the feature or model level will retain more information than at the score level. This paper presents a new strategy to build and fuse parallel phone recognizers (PPR). This is achieved by training multiple acoustic diversified phone recognizers and fusing at the feature level. The phone recognizers are trained on the same speech data but using different acoustic features and model training techniques. For the acoustic features, Mel-frequency cepstral coefficients (MFCC) and perceptual linear prediction (PLP) are both employed. In addition, a new time-frequency cepstrum (TFC) feature is proposed to extract complementary acoustic information. For the model training, we examine the use of the maximum likelihood and feature minimum phone error methods to train complementary acoustic models. In this study, we fuse phonotactic features of the acoustic diversified phone recognizers using a simple linear fusion method to build the PPRVSM system. A novel logistic regression optimized weighting (LROW) approach is introduced for fusion factor optimization. The experimental results show that fusion at the feature level is more effective than at the score level. And the proposed system is competitive with the traditional PPRVSM. Finally, the two systems are combined for further improvement. The best performing system reported in this paper achieves an equal error rate (EER) of 1.24%, 4.98% and 14.96% on the NIST 2007 LRE 30-second, 10-second and 3-second evaluation databases, respectively, for the closed-set test condition.

It has been shown that power control is an efficient approach to achieve the quality of service (QoS) requirement in wireless networks. In this letter, we present a utility function that denotes the QoS and energy efficiency of each wireless terminal. We propose a framework of power control based on the game theory for the QoS of wireless mesh networks (WMNs). In this framework, all players do their best to maximize their own utility. Furthermore, we present a Nash Equilibrium (NE) point of the power control game. We prove that the equilibrium is inefficient, and we propose a distributed power control algorithm that improves the total utility with respect to the NE point. Finally, the proposed framework is evaluated by a numerical experiment, the results of which show the rationality of our system model and the efficiency of our power control algorithm.

This letter presents an experiment for estimating accurate state in distributed power systems. This letter employs a technique that combines a projected Jacobi method with a parallel dual-type method to solve the distributed state estimation with constraints problems. Via numerous tests, this letter demonstrates the efficiency of the proposed method on the IEEE 118-bus with four subsystems in a PC network.

A regulation of converters connected in parallel is discussed considering their stored energy and passivity characteristics. From the viewpoint of stored energy, a new regulation method to conserve and share the stored energy can be found. The energy stored in inductors and capacitors is transferred to loads so that the load keeps the energy dissipation constant. Though numerical simulation, the method is validated for a parallel converter system.

This paper presents a syntax-based framework for gap resolution in analytic languages. CCG, reputable for dealing with deletion under coordination, is extended with a memory mechanism similar to the slot-and-filler mechanism, resulting in a wider coverage of syntactic gaps patterns. Though our grammar formalism is more expressive than the canonical CCG, its generative power is bounded by Partially Linear Indexed Grammar. Despite the spurious ambiguity originated from the memory mechanism, we also show that its probabilistic parsing is feasible by using the dual decomposition algorithm.

Due to the increased preservation efforts, large amounts of past Web data have been stored in Web archives and other archival repositories. Utilizing this data can offer certain benefits to users, for example, it can facilitate page understanding. In this paper, we propose a system for interactive exploration of page histories. We demonstrate an application called Page History Explorer (PHE) for summarizing and visualizing histories of Web pages. PHE portrays the overview of page evolution, characterizes its typical content over time and lets users observe page histories from different viewpoints. In addition, it enables flexible comparison of histories of different pages.

Scalability and availability are the key features of parallel database systems. To realize scalability, many dynamic load-balancing methods with data placement and parallel index structures on shared-nothing parallel infrastructure have been proposed. Data migration with range-partitioned placement using a parallel Btree is one solution. The combination of range partitioning and chained declustered replicas provides high availability (HA) while preserving scalability. However, independent treatment of the primary and backup data in each node requires long failover times. We propose a novel method for the compound treatment of chained declustered replicas using a parallel Btree, termed the Fat-Btree. In the proposed method, a single Fat-Btree provides access paths to both the primary and backup data of all processor elements (PEs), which greatly reduces failover time. Moreover, these access paths overlap between two neighboring PEs, which enables dynamic load balancing without physical data migration by dynamically redirecting the access paths. In addition, this compound treatment improves memory space utilization to enable index processing with good scalability. Experiments using PostgreSQL on a 160-node PC cluster demonstrate the effectiveness of the high scalability and availability of our proposed method.

Semiconducting polymers, poly(1,4-phenylene) (PPP) and poly(4-diphenylaminostyrene) (PDAS), which are soluble to organic solvents, were synthesized and were deposited by means of electrospray deposition (ESD). The ESD generated spherical shells of diameters ranging from a few to several tens of microns. The shells consisted of coagulation of nanometric particles of the semiconducting polymers. Formation of the shells was largely influenced by the concentration of spray solution. It was also found that the formation of shells can be achieved with various types of soluble polymers.

The proposed scheduling scheme minimizes the mean energy consumption of a real-time parallel task, where the task has the probabilistic computation amount and can be executed concurrently on multiple cores. The scheme determines a pertinent number of cores allocated to the task execution and the instant frequency supplied to the allocated cores. Evaluation shows that the scheme saves manifest amount of the energy consumed by the previous method minimizing the mean energy consumption on a single core.

In this paper, we propose a novel lattice structure of two dimensional (2D) nonseparable linear-phase paraunitary filter banks (LPPUFBs) called 2D GenLOT. Muramatsu et al. have previously proposed a lattice structure of 2D nonseparable LPPUFBs which have efficient frequency response. However, the proposed structure requires less number of design parameters and computational costs than the conventional one. Through some design examples and simulation results, we show that both filter banks have comparable frequency response and coding gain.

This paper proposes a synthesis method of 2-channel IIR paraunitary filter banks by successive extraction of 2-port lattice sections. When a power symmetry transfer function is given, a filter bank is realized as cascade of paraunitary 2-port lattice sections. The method can synthesize both odd- and even-order filters with Butterworth or elliptic characteristics. The number of multiplications per second can also be reduced.

In this paper, we study the minimum spanning tree problem with label selection, that is, the problem of finding a minimum spanning tree of a vertex-labeled graph where the weight of each edge may vary depending on the selection of labels of vertices at both ends. The problem is especially important as the application to mathematical OCR. It is shown that the problem is NP-hard. However, for the application to mathematical OCR, it is sufficient to deal with only graphs with small tree-width. In this paper, a linear-time algorithm for series-parallel graphs is presented. Since the minimum spanning tree problem with label selection is closely related to the generalized minimum spanning tree problem, their relation is discussed.