An algorithm for estimating sinusoidal parameters is presented. In this paper, it is assumed that an observed signal is a single sinusoidal signal contaminated by white Gaussian noise. Based on this assumption, the sinusoidal parameters can be found by minimizing a cost function using the mean squared error (MSE) between the observed signal and a sinusoidal signal with arbitrary sinusoidal parameters. Because the cost function is nonlinear and not convex, it has undesirable local minima. To solve the minimization problem, we propose to use the roots of an algebraic equation. The algebraic equation is derived straightforwardly from the cost function. We show that the global solution is formulated by using the roots of the algebraic equation.

For an indoor area where a target node is tracked with anchor nodes, we can calculate the priori probability density functions (pdfs) on the distances between the target and anchor nodes by using its shape, three-dimensional sizes and anchor nodes locations. We call it “the area layout information (ALI)” and apply it for two indoor target tracking methods with received signal strength indication (RSSI) assuming a square location estimation area. First, we introduce the ALI to a target tracking method which tracks a target using the weighted sum of its past-to-present locations by a simple infinite impulse response (IIR) low pass filter. Second, we show that the ALI is applicable to a target tracking method with a particle filter where the motion of the target is nonlinearly modelled. The performances of the two tracking methods are evaluated by not only computer simulations but also experiments. The results demonstrate that the use of ALI can successfully improve the location estimation performance of both target tracking methods, without huge increase of computational complexity.

In this letter, a novel adaptive total variation (ATV) model is proposed for image inpainting. The classical TV model is a partial differential equation (PDE)-based technique. While the TV model can preserve the image edges well, it has some drawbacks, such as staircase effect in the inpainted image and slow convergence rate. By analyzing the diffusion mechanism of TV model and introducing a new edge detection operator named difference curvature, we propose a novel ATV inpainting model. The proposed ATV model can diffuse the image information smoothly and quickly, namely, this model not only eliminates the staircase effect but also accelerates the convergence rate. Experimental results demonstrate the effectiveness of the proposed scheme.

Manufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divide-and-conquer. It is a distributed algorithm, and each router guarantees fault-tolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37% compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

Since the release of human genome sequences, one of the most important research issues is about indexing the genome sequences, and the suffix tree is most widely adopted for that purpose. The traditional suffix tree construction algorithms suffer from severe performance degradation due to the memory bottleneck problem. The recent disk-based algorithms also provide limited performance improvement due to random disk accesses. Moreover, they do not fully utilize the recent CPUs with multiple cores. In this paper, we propose a fast algorithm based on `divide-and-conquer' strategy for indexing the human genome sequences. Our algorithm nearly eliminates random disk accesses by accessing the disk in the unit of contiguous chunks. In addition, our algorithm fully utilizes the multi-core CPUs by dividing the genome sequences into multiple partitions and then assigning each partition to a different core for parallel processing. Experimental results show that our algorithm outperforms the previous fastest DIGEST algorithm by up to 10.5 times.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

We study nn random symmetric matrices whose entries above the diagonal are iid random variables each of which takes 1 with probability p and 0 with probability 1-p, for a given density parameter p=α/n for sufficiently large α. For a given such matrix A, we consider a matrix A ' that is obtained by removing some rows and corresponding columns with too many value 1 entries. Then for this A', we show that the largest eigenvalue is asymptotically close to α+1 and its eigenvector is almost parallel to all one vector (1,...,1).

A perfect sequence is a sequence having an impulsive autocorrelation function. Perfect sequences have several applications, such as CDMA, ultrasonic imaging, and position control. A parameterization of a perfect sequence is presented in the present paper. We treat a set of perfect sequences as a zero set of quadratic equations and prove a decomposition law of perfect sequences. The decomposition law reduces the problem of the parameterization of perfect sequences to the problem of the parameterization of quasi-perfect sequences and the parameterization of perfect sequences of short length. The parameterization of perfect sequences for simple cases and quasi-perfect sequences should be helpful in obtaining a parameterization of perfect sequences of arbitrary length. According to our theorem, perfect sequences can be represented by a sum of trigonometric functions.

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

P. Kirchberger proved that, for a finite subset X of Rd such that each point in X is painted with one of two colors, if every d+2 or fewer points in X can be separated along the colors, then all the points in X can be separated along the colors. In this paper, we show a more colorful theorem.

In this letter, we propose a Partially Observable Markov Decision Process (POMDP) based Distributed Adaptive Opportunistic Spectrum Access (DA-OSA) Strategy for Cognitive Ad Hoc Networks (CAHNs). In each slot, the source and destination choose a set of channels to sense and then decide the transmission channels based on the sensing results. In order to maximize the throughput for each link, we use the theories of sequential decision and optimal stopping to determine the optimal sensing channel set. Moreover, we also establish the myopic policy and exploit the monotonicity of the reward function that we use, which can be used to reduce the complexity of the sequential decision.

Lattice decoding in statistical machine translation (SMT) is useful in speech translation and in the translation of German because it can handle input ambiguities such as speech recognition ambiguities and German word segmentation ambiguities. In this paper, we show that lattice decoding is also useful for handling input variations. “Input variations” refers to the differences in input texts with the same meaning. Given an input sentence, we build a lattice which represents paraphrases of the input sentence. We call this a paraphrase lattice. Then, we give the paraphrase lattice as an input to a lattice decoder. The lattice decoder searches for the best path of the paraphrase lattice and outputs the best translation. Experimental results using the IWSLT dataset and the Europarl dataset show that our proposed method obtains significant gains in BLEU scores.

In this paper, we propose a robust state estimation method using a particle filter (PF) for a class of nonlinear systems which have stochastic parameter uncertainties. A robust PF was designed using prediction and correction structure. The proposed PF draws particles from a simple proposal density function and corrects the particles with particle-wise correction gains. We present a method to obtain an error variance of each particle and its upper bound, which is minimized to determine the correction gain. The proposed method is less restrictive on system nonlinearities and noise statistics; moreover, it can be applied regardless of system stability. The effectiveness of the proposed robust PF is illustrated via an example based on Chua's circuit.

A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.

A zig-zag Gardner algorithm with parallel architecture is presented in this letter. This algorithm performs timing adjustment in each individual burst independently for high speed wireless burst communication with a short guard. Over sampling data are stored in RAM initially and read forward and backward alternately later. The proposed algorithm has distinct symmetric characteristic in the forward and backward process, which makes the alternate sequences achieve nearly the same effect as a continuous sequence. The performance of the proposed algorithm is very close to the theoretical curve.

We describe a parameter estimation method for a target object in an area that sensors monitor. The parameters to be estimated are the perimeter length, size, and parameter determined by the interior angles of the target object. The estimation method does not use sensor location information, only the binary information on whether each sensor detects the target object. First, the sensing area of each sensor is assumed to be line-segment-shaped, which is a model of an infrared distance measurement sensor. Second, based on the analytical results of assuming line-segment-shaped sensing areas, we developed a unified equation that works with general sensing areas and general target-object shapes to estimate the parameters of the target objects. Numerical examples using computer simulation show that our method yields accurate results.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

There are a great amount of various resources described in many different ways for service oriented grid environment, while traditional grid resource discovery methods could not fit more complex future grid system. Therefore, this paper proposes a novel grid resource discovery method based on association rule hypergraph partitioning algorithm which analyzes user behavior in history transaction records to provide personality service for user. And this resource discovery method gives a new way to improve resource retrieval and management in grid research.