In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

We propose a Junction-Based Traffic Aware Routing (JTAR) protocol for Vehicular Ad Hoc Networks (VANETs) in sparse urban environments. A traffic aware optimum junction selection solution is adopted in packet-forwarding, and a metric named critical-segment is defined in recovery strategy. Simulation results show that JTAR can efficiently increase the packet delivery ratio and reduce the delivery delay.

The k-edge-connectivity augmentation problem with bipartition constraints (kECABP, for short) is defined by “Given an undirected graph G=(V, E) and a bipartition π = {VB, VW} of V with VB ∩ VW = ∅, find an edge set Ef of minimum cardinality, consisting of edges that connect VB and VW, such that G'=(V, E ∪ Ef) is k-edge-connected.” The problem has applications for security of statistical data stored in a cross tabulated table, and so on. In this paper we propose a fast algorithm for finding an optimal solution to (σ + 1)ECABP in O(|V||E| + |V2|log |V|) time when G is σ-edge-connected (σ > 0), and show that the problem can be solved in linear time if σ ∈ {1, 2}.

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have several appealing properties regarding decoding, storage requirements and encoding aspects. In this paper, we focus on the QC LDPC codes over GF(q) whose parity-check matrices have fixed column weight j = 2. By investigating two subgraphs in the Tanner graphs of the corresponding base matrices, we derive two upper bounds on the minimum Hamming distance for this class of codes. In addition, a method is proposed to construct QC LDPC codes over GF(q), which have good Hamming distance distributions. Simulations show that our designed codes have good performance.

Magnetic particle imaging (MPI), in which the nonlinear interaction between internally administered magnetic nanoparticles (MNPs) and electromagnetic waves irradiated from outside of the body is utilized, has attracted attention for its potential to achieve early diagnosis of diseases such as cancer. In MPI, the local magnetic field distribution is scanned, and the magnetization signal from MNPs within a selected region is detected. However, the signal sensitivity and image resolution are degraded by interference from magnetization signals generated by MNPs outside of the selected region, mainly because of imperfections (limited gradients) in the local magnetic field distribution. Here, we propose new methods based on correlation information between the observed signal and the system function–defined as the interaction between the magnetic field distribution and the magnetizing properties of MNPs. We performed numerical analyses and found that, although the images were somewhat blurred, image artifacts could be significantly reduced and accurate images could be reconstructed without the inverse-matrix operation used in conventional image reconstruction methods.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

Obtaining a compact representation of a large-size feature map built by mapper robots is a critical issue in recent mobile robotics. This “map compression” problem is explored from a novel perspective of dictionary-based data compression techniques in the paper. The primary contribution of the paper is the proposal of the dictionary-based map compression approach. A map compression system is presented by employing RANSAC map matching and sparse coding as building blocks. The effectiveness levels of the proposed techniques is investigated in terms of map compression ratio, compression speed, the retrieval performance of compressed/decompressed maps, as well as applications to the Kolmogorov complexity.

For Doppler parameter estimation of forward-looking SAR, the third-order Doppler parameter can not be neglected. In this paper, the azimuth signal of the transmitter fixed bistatic forward-looking SAR is modeled as a cubic polynomial phase signal (CPPS) and multiple time-overlapped CPPSs, and the modified cubic phase function is presented to estimate the third-order Doppler parameter. By combining the cubic phase function (CPF) with Radon transform, the method can give an accurate estimation of the third-order Doppler parameter. Simulations validate the effectiveness of the algorithm.

In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.

This paper presents a novel method for robust object tracking in video sequences using a hybrid feature-based observation model in a particle filtering framework. An ideal observation model should have both high ability to accurately distinguish objects from the background and high reliability to identify the detected objects. Traditional features are better at solving the former problem but weak in solving the latter one. To overcome that, we adopt a robust and dynamic feature called Grayscale Arranging Pairs (GAP), which has high discriminative ability even under conditions of severe illumination variation and dynamic background elements. Together with the GAP feature, we also adopt the color histogram feature in order to take advantage of traditional features in resolving the first problem. At the same time, an efficient and simple integration method is used to combine the GAP feature with color information. Comparative experiments demonstrate that object tracking with our integrated features performs well even when objects go across complex backgrounds.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

We quantitatively evaluate how sampling and spatio/temporal granularity in traffic monitoring affect the detectability of anomalous traffic. Those parameters also affect the monitoring burden, so network operators face a trade-off between the monitoring burden and detectability and need to know which are the optimal paramter values. We derive equations to calculate the false positive ratio and false negative ratio for given values of the sampling rate, granularity, statistics of normal traffic, and volume of anomalies to be detected. Specifically, assuming that the normal traffic has a Gaussian distribution, which is parameterized by its mean and standard deviation, we analyze how sampling and monitoring granularity change these distribution parameters. This analysis is based on observation of the backbone traffic, which exhibits spatially uncorrelated and temporally long-range dependence. Then we derive the equations for detectability. With those equations, we can answer the practical questions that arise in actual network operations: what sampling rate to set to find the given volume of anomaly, or, if the sampling is too high for actual operation, what granularity is optimal to find the anomaly for a given lower limit of sampling rate.

Accelerator cores in low-power heterogeneous processors have on-chip local memories to enable parallel data access. The memory capacities of the local memories are very small. Therefore, the data should be transferred from the global memory to the local memories many times. These data transfers greatly increase the total processing time. Memory allocation technique to increase the data sharing is a good solution to this problem. However, when using reconfigurable cores, the data must be shared among multiple contexts. However, conventional context partitioning methods only consider how to reuse limited hardware resources in different time slots. They do not consider the data sharing. This paper proposes a context partitioning method to share both the hardware resources and the local memory data. According to the experimental results, the proposed method reduces the processing time by more than 87% compared to conventional context partitioning techniques.

Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

This paper presents an ultra-wideband (UWB) bandpass filter (BPF) with sharp attenuation slope characteristics. The circuit structure consists of an inter-digital finger resonator, parallel-coupled lines and phase matching line. The design of the bandwidth was described by using the even and odd mode characteristic impedances in the resonator structure. The parallel-coupled lines were also designed in the same manner. The parameters of the resonator and two parallel-coupled lines in combination as the BPF were then optimized by the simulation with HFSS. The designed BPF was experimentally fabricated and its measured performances showed the bandwidth from 3.6 to 10 GHz with the 20 dB outband rejection. For the U.S. UWB band design, the matching line was inserted between the two parallel-coupled lines. The matching at both band edges was then qualitatively analyzed on the smithchart. The HFSS simulation results of the structure realized the bandwidth from 3.1 to 10.6 GHz with sharp attenuation slope characteristics for SWR < 2.0. The measurement results agree well with the simulation results.

A Mur type analytical absorbing boundary condition (A-ABC), which is based on the one-dimensional one-way wave equation, is proposed for multidimensional wave analysis by introducing the directional splitting technique. This new absorbing boundary condition is expansion of the first-order Mur. The absorbing ability, required memory, and calculation speed of the Mur type A-ABC are evaluated by comparison with those of conventional ABCs. The result indicated that absorbing ability of the proposed ABC is higher than the first-order Mur and lower than the second-order Mur at large incident angle. While, our proposed ABC has advantage in both required memory and calculation speed by comparison with the second-order Mur. Thus, effectivity of the proposed Mur type A-ABC is shown.

To assess the performance of maximum-likelihood (ML) based Nakagami m parameter estimators, current methods rely on Monte Carlo simulation. In order to enable the analytical performance evaluation of ML-based m parameter estimators, we study the statistical properties of a parameter Δ, which is defined as the log-ratio of the arithmetic mean to the geometric mean for Nakagami-m fading power. Closed-form expressions are derived for the probability density function (PDF) of Δ. It is found that for large sample size, the PDF of Δ can be well approximated by a two-parameter Gamma PDF.

In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

In next-generation networks, ultra-high speed transfer capability will become necessary to support a variety of advanced multimedia services. The Optical Wavelength Division Multiplexing (WDM) network is seen as one of promising networks. To deal with various multimedia services, the network should support not only unicast transmission but also multicast transmission. However, IP multicast has several problems, for example, all routers must have multicast functions. IP multicast needs routers with high overheads and excessive energy consumption. Hence, optical multicasting in optical WDM networks is a promising solution for future internet services. A tree-shared multicasting concept has been proposed to support multicast transmissions in optical WDM networks. This method assembles multiple multicast traffic streams into one burst and the burst is delivered using a shared-tree. However, this method can not be applied to dynamic multicasting. This paper proposes a novel WDM multicast design method for dynamic traffic demand using multiple shared-trees, which includes shared-tree generation/selection and wavelength assignment, for the purpose of simplifying the routing process and receiving multicast traffic efficiently. We evaluate its performance from the viewpoints of the burst loss probability and the number of redundant and useless transfers whose data is discarded at the egress edge nodes.

In this letter, we propose a distributed switch-and-stay combining network with partial relay selection and show that the system spectral efficiency can be improved via adaptive modulation. Analytical expressions for the achievable spectral efficiency and average bit error rate of the proposed system over Rayleigh fading channels are derived for an arbitrary switching threshold. Numerical results are gathered to substantiate the analytical derivation showing that in terms of spectral efficiency, the system with single relay outperforms that with more than one relay at high signal-to-noise ratios (SNRs) and the optimal switching threshold can significantly improve the system performance at medium SNRs.