In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

In this paper, we propose a new technique for the transient scattering problem of periodically arrayed dispersion media for the TE case by using a combination of the Fourier series expansion method (FSEM) and the fast inversion Laplace transform (FILT) method, and analyze the pulse response for various widths of the dispersion media. As a result, we clarified the influence of the dispersion media with an air region on the resulting waveform.

The large computational complexity makes stereo matching a big challenge in real-time application scenario. The problem of stereo matching in a video sequence is slightly different with that in a still image because there exists temporal correlation among video frames. However, no existing method considered temporal consistency of disparity for algorithm acceleration. In this work, we proposed a scheme called the dynamic disparity range (DDR) to optimize matching cost calculation and cost aggregation steps by narrowing disparity searching range, and a scheme called temporal cost aggregation path to optimize the cost aggregation step. Based on the schemes, we proposed the DDR-SGM and the DDR-MCCNN algorithms for the stereo matching in video sequences. Evaluation results showed that the proposed algorithms significantly reduced the computational complexity with only very slight loss of accuracy. We proved that the proposed optimizations for the stereo matching are effective and the temporal consistency in stereo video is highly useful for either improving accuracy or reducing computational complexity.

Design of an equivalent slew-rate monolithic pulse generator using bipolar-CMOS-DMOS (BCD) technology for medical ultrasound transmitters is presented in this paper. The pulse generator employs a floating capacitive coupling level-shifter architecture to produce a high-voltage (Vpp=80V) output. The performance of equivalent slew-rate in the rising and falling edge is achieved by carefully choosing the value of coupling capacitors and the size of the final stage high-voltage MOSFETs of the pulse generator. The measured output pulses show the rising and falling time of 8.6nsec and 8.5nsec, respectively with second harmonic distortion down to -40dBc, indicating the designed pulse generator can be used for advanced ultrasonic harmonic imaging systems.

A multi-carrier and blind shift-frequency jamming(MCBSFJ) against the pulsed compression radar with order-statistic (OS) constant false alarm rate (CFAR) detector is proposed. Firstly, according to the detection principle of the OS-CFAR detector, the design requirements for jamming signals are proposed. Then, some key parameters of the jamming are derived based on the characteristics of the OS-CFAR detector. As a result, multiple false targets around the real target with the quantity, amplitude and space distribution which can be controlled are produced. The simulation results show that the jamming method can reduce the detection probability of the target effectively.

For the further scaling and lower voltage applications of nonvolatile ferroelectric memory, the effect of Kr/O2 sputtering for SrBi2Ta2O9 (SBT) thin film formation was investigated utilizing a SrBi2Ta2O9 target. The 80-nm-thick SBT films were deposited by radio-frequency (RF) magnetron sputtering on Pt/Ti/SiO2/Si(100). Compared with Ar/O2 sputtering, the ferroelectric properties such as larger remnant polarization (Pr) of 3.2 μC/cm2 were observed with decrease of leakage current in case of Kr/O2 sputtering. X-ray diffraction (XRD) patterns indicated that improvement of the crystallinity with suppressing pyrochlore phases and enhancing ferroelectric phases was realized by Kr/O2 sputtering.

Affine projection sign algorithm (APSA) is an important adaptive filtering method to combat the impulsive noisy environment. However, the performance of APSA is poor, if its regularization parameter is not well chosen. We propose a variable regularization APSA (VR-APSA) approach, which adopts a gradient-based method to recursively reduce the norm of the a priori error vector. The resulting VR-APSA leverages the time correlation of both the input signal matrix and error vector to adjust the value of the regularization parameter. Simulation results confirm that our algorithm exhibits both fast convergence and small misadjustment properties.

Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FPGAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

Wireless powered communication networks (WPCNs) utilize the wireless energy transfer (WET) technique to facilitate the wireless information transmission (WIT) of nodes. We propose a two-step iterative algorithm to maximize the sum throughput of the users in a MIMO WPCN with discrete signal inputs. Firstly, the optimal solution of a convex power allocation problem can be found given a fixed time allocation; Secondly, a semi closed form solution for the optimal time allocation is obtained when fixing the power allocation matrix. By optimizing the power allocation and time allocation alternately, the two-step algorithm converges to a local optimal point. Simulation results show that the proposed algorithm outperforms the conventional schemes, which consider only Gaussian inputs.

A low complexity channel estimation scheme using data-dependent superimposed training (DDST) is proposed in this paper, where the pilots are inserted in more than one block, rather than the single block of the original DDST. Comparing with the original DDST (which improves the performance of channel estimation at the cost of huge computational overheads), the proposed DDST scheme improves the performance of channel estimation with only a slight increase in the consumption of computation resources. The optimal precoder is designed to minimize the data distortion caused by the rank-deficient precoding. The optimal pilots and placement are also provided to improve the performance of channel estimation. In addition, the impact of power allocation between the data and pilots on symbol detection is analyzed, the optimal power allocation scheme is derived to maximize the effective signal-to-noise ratio at the receiver. Simulation results are presented to show the computational advantage of the proposed scheme, and the advantages of the optimal pilots and power allocation scheme.

Accounting for the exponential increase in security threats, the development of new defense strategies for pervasive environments is acquiring an ever-growing importance. The expected avalanche of heterogeneous IoT devices which will populate our industrial factories and smart houses will increase the complexity of managing security requirements in a comprehensive way. To this aim, cloud-based security services are gaining notable impetus to provide security mechanisms according to Security-as-a-Service (SECaaS) model. However, the deployment of security applications in remote cloud data-centers can introduce several drawbacks in terms of traffic overhead and latency increase. To cope with this, Edge Computing can provide remarkable advantages avoiding long routing detours. On the other hand, the limited capabilities of edge node introduce potential constraints in the overall management. This paper focuses on the provisioning of virtualized security services in resource-constrained edge nodes by leveraging lightweight virtualization technologies. Our analysis aims at shedding light on the feasibility of container-based security solutions, thus providing useful guidelines towards the orchestration of security at the edge. Our experiments show that the overhead introduced by the containerization is very light.

Sectors in the airspace are units of the air traffic control. For airspace traffic data consists of the location of each aircraft with timestamp, we propose an efficient method to identify the sector where each aircraft lies.

This paper proposes a novel low complexity lattice reduction-aided iterative receiver for overloaded MIMO. Novel noise cancellation is proposed that increases an equivalent channel gain with a scalar gain introduced in this paper, which results in the improvement of the signal to noise power ratio (SNR). We theoretically analyze the performance of the proposed receiver that the lattice reduction raises the SNR of the detector output signals as the scalar gain increases, when the Lenstra-Lenstra-Lova's (LLL) algorithm is applied to implement the lattice reduction. Because the SNR improvement causes the scalar gain to increase, the performance is improved by iterating the reception process. Computer simulations confirm the performance. The proposed receiver attains a gain of about 5dB at the BER of 10-4 in a 6×2 overloaded MIMO channel. Computational complexity of the proposed receiver is about 1/50 as much as that of the maximum likelihood detection (MLD).

The needs for ultra-high speed short- to medium-reach optical fiber links beyond 100-Gbit/s is becoming larger and larger especially for intra and inter-data center applications. In recent intensity-modulated/direct-detection (IM/DD) high-speed optical transceivers with the channel bit rate of 50 and/or 100 Gbit/s, multilevel pulse amplitude modulation (PAM) is finally adopted to lower the signaling speed. To further increase the transmission capacity for the next-generation optical transceivers, various signaling techniques have been studied, especially thanks to advanced digital signal processing (DSP). In this paper, we review various signaling technologies proposed so far for short-to-medium reach applications.

A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.

The IEEE 802.11p Enhanced Distributed Channel Access (EDCA) is a standardization for vehicle-to-vehicle and road-to-vehicle communications. The saturated throughputs of the IEEE 802.11p EDCA obtained from previous analytical expressions differ from those of simulations. The purpose of this paper is to explain the reason why the differences appear in the previous analytical model of the EDCA. It is clarified that there is a special state wherein the Backoff Timer (BT) is decremented in the first time slot of after a frame transmission, which cannot be expressed in the previous Markov model. In addition, this paper proposes modified Markov models, which allow the IEEE 802.11p EDCA to be correctly analyzed. The proposed models describe BT-decrement procedure in the first time slot accurately by adding new states to the previous model. As a result, the proposed models provide accurate transmission probabilities of network nodes. The validity of the proposed models is confirmed by the quantitative agreements between analytical predictions and simulation results.

Approximate computing is a promising paradigm to realize fast, small, and low power characteristics, which are essential for modern applications, such as Internet of Things (IoT) devices. This paper proposes the Carry-Predicting Adder (CPredA), an approximate adder that is scalable relative to accuracy and power consumption. The proposed CPredA improves the accuracy of a previously studied adder by performing carry prediction. Detailed simulations reveal that, compared to the existing approximate adder, accuracy is improved by approximately 50% with comparable energy efficiency. Two application-level evaluations demonstrate that the proposed approximate adder is sufficiently accurate for practical use.

The influence of pump phase error on phase-sensitive optical amplifier (PSA) repeaters and the waveform degradation due to chromatic dispersion and fiber nonlinearities in the optical multi-relay transmission of quadrature phase-shift keying phase-conjugated twin waves are considered theoretically. First, the influence of noise from the pump phase error, optical local oscillator, receiver, and the amplified spontaneous-emission (ASE) in PSA repeaters is investigated with the assumption that transmission fibers are linear lossy channels. The bit-error rate (BER) is estimated as a function of the signal-to-noise ratio, and the relationship between the number of transmission relays and the fiber launch power is clarified. Waveform degradation due to chromatic dispersion and the optical fiber nonlinearities in transmission fibers are investigated with the noiseless condition, and the maximum repeatable number as a function of the fiber launch power is calculated. Finally, we show the relationship among the maximum repeatable number, standard deviation of pump phase error in PSA repeaters, and the fiber launch power to clarify the optimum transmission condition with consideration of the noise and the waveform degradation.

In this paper, we briefly review the concept of superconducting quantum computers and discuss their hardware architecture. We also describe the necessary technologies for the development of a medium-scale quantum computer with more than tens of thousands of quantum bits.

The recent rapid increase in the scale of superconducting quantum computing systems greatly increases the demand for qubit control by digital circuits operating at qubit temperatures. In this paper, superconducting digital circuits, such as single-flux quantum and adiabatic quantum flux parametron circuits are described, that are promising candidates for this purpose. After estimating their energy consumption and speed, a conceptual overview of the superconducting electronics for controlling a multiple-qubit system is provided, as well as some of its component circuits.