The generalized spatial modulation (GSM) is a new transmission technique that can realize high-performance multiple-input multiple-output (MIMO) communication systems with a low RF complexity. This paper presents an efficient sphere decoding method used to perform the symbol detection for the generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems. In the proposed method, the cost metric is modified so that it does not include the cancellation of the nonexistent interference. The modified cost metric can be computed by formulating a detection tree that has a regular structure representing the transmit antenna combinations as well as the symbol vectors, both of which are detected efficiently by finding the shortest path on the basis of an efficient tree search algorithm. As the tree search algorithm is performed for the regular detection tree to compute the modified but mathematically-equivalent cost metric, the efficiency of the sphere decoding is improved while the bit-error rate performance is not degraded. The simulation results show that the proposed method reduces the complexity significantly when compared with the previous method: for the 6×6 64QAM GSM-MIMO system with two active antennas, the average reduction rate of the complexity is as high as 45.8% in the count of the numerical operations.

Cooperative caching is a key technique to reduce rapid growing video-on-demand's traffic by aggregating multiple cache storages. Existing strategies periodically calculate a sub-optimal allocation of the content caches in the network. Although such technique could reduce the generated traffic between servers, it comes with the cost of a large computational overhead. This overhead will be the cause of preventing these caches from following the rapid change in the access pattern. In this paper, we propose a light-weight scheme for cooperative caching by grouping contents and servers with color tags. In our proposal, we associate servers and caches through a color tag, with the aim to increase the effective cache capacity by storing different contents among servers. In addition to the color tags, we propose a novel hybrid caching scheme that divides its storage area into colored LFU (Least Frequently Used) and no-color LRU (Least Recently Used) areas. The colored LFU area stores color-matching contents to increase cache hit rate and no-color LRU area follows rapid changes in access patterns by storing popular contents regardless of their tags. On the top of the proposed architecture, we also present a new routing algorithm that takes benefit of the color tags information to reduce the traffic by fetching cached contents from the nearest server. Evaluation results, using a backbone network topology, showed that our color-tag based caching scheme could achieve a performance close to the sub-optimal one obtained with a genetic algorithm calculation, with only a few seconds of computational overhead. Furthermore, the proposed hybrid caching could limit the degradation of hit rate from 13.9% in conventional non-colored LFU, to only 2.3%, which proves the capability of our scheme to follow rapid insertions of new popular contents. Finally, the color-based routing scheme could reduce the traffic by up to 31.9% when compared with the shortest-path routing.

One of the problems associated with voice conversion from a nonparallel corpus is how to find the best match or alignment between the source and the target vector sequences without linguistic information. In a previous study, alignment was achieved by minimizing the distance between the source vector and the transformed vector. This method, however, yielded a sequence of feature vectors that were not well matched with the underlying speaker model. In this letter, the vectors were selected from the candidates by maximizing the overall likelihood of the selected vectors with respect to the target model in the HMM context. Both objective and subjective evaluations were carried out using the CMU ARCTIC database to verify the effectiveness of the proposed method.

Hardware implementation of neural networks usually have high computational complexity that increase exponentially with the size of a circuit, leading to more uncertain and unreliable circuit performance. This letter presents a novel Radial Basis Function (RBF) neural network based on parallel fault tolerant stochastic computing, in which number is converted from deterministic domain to probabilistic domain. The Gaussian RBF for middle layer neuron is implemented using stochastic structure that reduce the hardware resources significantly. Our experimental results from two pattern recognition tests (the Thomas gestures and the MIT faces) show that the stochastic design is capable to maintain equivalent performance when the stream length set to 10Kbits. The stochastic hidden neuron uses only 1.2% hardware resource compared with the CORDIC algorithm. Furthermore, the proposed algorithm is very flexible in design tradeoff between computing accuracy, power consumption and chip area.

A TM010 cavity power combiner is presented, which achieves direct interface to microstrip lines via magnetic field coupling. A prototype is fabricated and its S-matrix measured. From the S-parameters we calculate that it shows less than 0.85 dB insertion loss over 250 MHz bandwidth at X-band. The return power to the input ports is less than -15 dB over this bandwidth. We verify the insertion loss estimation using S-matrix, by measuring transmission S-parameter of a concatenated 2-port divider-combiner network. Similarly analyzed is the case of performance of power combiner when one of the input fails. We find that we can achieve graceful degradation provided we ensure some particular reflection phase at the degraded port.

A Tikhonov regularized RLS algorithm with an exponential weighting factor, i.e., a leaky RLS (LRLS) algorithm was proposed by the author. A quadratic version of the LRLS algorithm also exists in the literature of adaptive filters. In this letter, a cubic version of the LRLS filter which is computationally efficient is proposed when the length of the adaptive filter is short. The proposed LRLS filter includes only a divide per iteration although its multiplications and additions increase in number. Simulation results show that the proposed LRLS filter is faster for its short length than the existing quadratic version of the LRLS filter.

This paper considers a design method of a discrete-time adaptive output feedback control system with a feedforward input based on almost strict positive realness (ASPR-ness). The proposed scheme utilizes the property of ASPR of the controlled plant, and the reference signal is used as feedforward input. The parallel feedforward compensator (PFC) which renders an ASPR augmented controlled plant is also investigated. Besides, it is shown that the output of original plant can track reference signal perfectly without any steady state error. The effectiveness of the proposed scheme is confirmed through a pilot-scale temperature control system.

Object detection is an essential and expensive process in many computer vision systems. Standard off-the-shelf embedded processors are hard to achieve performance-power balance for implementation of object detection applications. In this work, we explore an Application Specific Instruction set Processor (ASIP) for object detection using Histogram of Oriented Gradients (HOG) feature. Algorithm simplifications are adopted to reduce memory bandwidth requirements and mathematical complexity without losing reliability. Also, parallel histogram generation and on-the-fly Support Vector Machine (SVM) calculation architecture are employed to reduce the necessary cycle counts. The HOG algorithm on the proposed ASIP was accelerated by a factor of 63x compared to the pure software implementation. The ASIP was synthesized for a standard 90nm CMOS library, with a silicon area of 1.31mm2 and 47.8mW power consumption at a 200MHz frequency. Our object detection processor can achieve 42 frames-per-second (fps) on VGA video. The evaluation and implementation results show that the proposed ASIP is both area-efficient and power-efficient while being competitive with commercial CPUs/DSPs. Furthermore, our ASIP exhibits comparable performance even with hard-wire designs.

Interconnection network is one of the inevitable components in parallel computers, since it is responsible to communication capabilities of the systems. It affects the system-level performance as well as the physical and logical structure of the systems. Although many studies are reported to enhance the interconnection network technology, we have to discuss many issues remaining. One of the most important issues is congestion management. In an interconnection network, many packets are transferred simultaneously and the packets interfere to each other in the network. Congestion arises as a result of the interferences. Its fast spreading speed seriously degrades communication performance and it continues for long time. Thus, we should appropriately control the network to suppress the congested situation for maintaining the maximum performance. Many studies address the problem and present effective methods, however, the maximal performance in an ideal situation is not sufficiently clarified. Solving the ideal performance is, in general, an NP-hard problem. This paper introduces particle swarm optimization (PSO) methodology to overcome the problem. In this paper, we first formalize the optimization problem suitable for the PSO method and present a simple PSO application as naive models. Then, we discuss reduction of the size of search space and introduce three practical variations of the PSO computation models as repetitive model, expansion model, and coding model. We furthermore introduce some non-PSO methods for comparison. Our evaluation results reveal high potentials of the PSO method. The repetitive and expansion models achieve significant acceleration of collective communication performance at most 1.72 times faster than that in the bursty communication condition.

The main contribution of this paper is to present an efficient GPU implementation of bulk computation of the CKY parsing for a context-free grammar, which determines if a context-free grammar derives each of a lot of input strings. The bulk computation is to execute the same algorithm for a lot of inputs in turn or at the same time. The CKY parsing is to determine if a context-free grammar derives a given string. We show that the bulk computation of the CKY parsing can be implemented in the GPU efficiently using Bitwise Parallel Bulk Computation (BPBC) technique. We also show the rule minimization technique and the dynamic scheduling method for further acceleration of the CKY parsing on the GPU. The experimental results using NVIDIA TITAN X GPU show that our implementation of the bitwise-parallel CKY parsing for strings of length 32 takes 395µs per string with 131072 production rules for 512 non-terminal symbols.

Streaming services that use TCP have increased; however, throughput is unstable due to congestion control caused by packet loss when TCP is used. Thus, TCP control to secure a required transmission rate for streaming communication using Forward Error Correction (FEC) technology (TCP-AFEC) has been proposed. TCP-AFEC can control the appropriate transmission rate according to network conditions using a combination of TCP congestion control and FEC. However, TCP-AFEC was not developed for wireless Local Area Network (LAN) environments; thus, it requires a certain time to set the appropriate redundancy and cannot obtain the required throughput. In this paper, we demonstrate the drawbacks of TCP-AFEC in wireless LAN environments. Then, we propose a redundancy setting method that can secure the required throughput for FEC, i.e., TCP-TFEC. Finally, we show that TCP-TFEC can secure more stable throughput than TCP-AFEC.

In this letter, we investigate the computation offloading problem in cloud based multi-robot systems, in which user weights, communication interference and cloud resource limitation are jointly considered. To minimize the system cost, two offloading selection and resource allocation algorithms are proposed. Numerical results show that the proposed algorithms both can greatly reduce the overall system cost, and the greedy selection based algorithm even achieves near-optimal performance.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

In this study, we consider techniques to search for high-rate punctured convolutional code (PCC) encoders by rearranging row vectors of identical-encoder generator matrices. One well-known method to obtain a good PCC encoder is to perform an exhaustive search of all candidates. However, this approach is time-intensive. An exhaustive search with a rate RG=1/2 original encoder requires a relatively short time, whereas that with an RG=1/3 or lower original encoder takes significantly longer. The encoders with lower-rate original encoders are expected to create better PCC encoders. Thus, this paper proposes a method that uses exhaustive search results with rate RG=1/2 original encoders, and rearranges row vectors of identical-encoder generator matrices to create PCCs with a lower rate original code. Further, we provide PCC encoders obtained by searches that utilize our method.

End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.

The ability to efficiently process exponentially increasing data remains a challenging issue for computer platforms. In legacy computing platforms, large amounts of data can cause performance bottlenecks at the I/O interfaces between CPUs and storage devices. To overcome this problem, the in-storage computing (ISC) technique is introduced, which offloads some of the computations from the CPUs to the storage devices. In this paper, we propose DiSC, a distributed in-storage computing platform using cost-effective hardware. First, we designed a general-purpose ISC device, a so-called DiSC endpoint, by combining an inexpensive single-board computer (SBC) and a hard disk. Second, a Mesos-based resource manager is adapted into the DiSC platform to schedule the DiSC endpoint tasks. To draw comparisons to a general CPU-based platform, a DiSC testbed is constructed and experiments are carried out using essential applications. The experimental results show that DiSC attains cost-efficient performance advantages over a desktop, particularly for searching and filtering workloads.

There is increasing interest in quantum computing, because of its enormous computing potential. A small number of powerful quantum algorithms have been proposed to date; however, the development of new quantum algorithms for practical use remains essential. Parallel computing with a neural network has successfully realized certain unique functions such as learning and recognition; therefore, the introduction of certain neural computing techniques into quantum computing to enlarge the quantum computing application field is worthwhile. In this paper, a novel quantum associative memory (QuAM) is proposed, which is achieved with a quantum neural network by employing adiabatic Hamiltonian evolution. The memorization and retrieval procedures are inspired by the concept of associative memory realized with an artificial neural network. To study the detailed dynamics of our QuAM, we examine two types of Hamiltonians for pattern memorization. The first is a Hamiltonian having diagonal elements, which is known as an Ising Hamiltonian and which is similar to the cost function of a Hopfield network. The second is a Hamiltonian having non-diagonal elements, which is known as a neuro-inspired Hamiltonian and which is based on interactions between qubits. Numerical simulations indicate that the proposed methods for pattern memorization and retrieval work well with both types of Hamiltonians. Further, both Hamiltonians yield almost identical performance, although their retrieval properties differ. The QuAM exhibits new and unique features, such as a large memory capacity, which differs from a conventional neural associative memory.

One of the key objectives of 5G is to evolve the current mobile network architecture from “one-fit-all” design model to a more customized and dynamically scaling one that enables the deployment of parallel systems, tailored to the service requirements on top of a shared infrastructure. Indeed, the envisioned 5G services may require different needs in terms of capacity, latency, bandwidth, reliability and security, which cannot be efficiently sustained by the same network infrastructure. Coming to address these customization challenges, network softwarization expressed through Software Defined Networking (SDN) programmable network infrastructures, Network Function Virtualization (NFV) running network functions as software and cloud computing flexibility paradigms, is seen as a possible panacea to addressing the variations in the network requirements posed by the 5G use cases. This will enable network flexibility and programmability, allow the creation and lifecycle management of virtual network slices tailored to the needs of 5G verticals expressed in the form of Mobile Virtual Network Operators (MVNOs) for automotive, eHealth, massive IoT, massive multimedia broadband. In this vein, this paper introduces a potential 5G architecture that enables the orchestration, instantiation and management of end-to-end network slices over multiple administrative and technological domains. The architecture is described from both the management and the service perspective, underlining the common functionality as well as how the response to the diversified service requirements can be achieved through proper software network components development.

Head-mounted displays (HMDs) and augmented reality (AR) are actively being studied. However, ordinary AR HMDs for visual assistance have a problem in which users have difficulty simultaneously focusing their eyes on both the real target object and the displayed image because the image can only be displayed at a fixed distance from an user's eyes in contrast to where the real object three-dimensionally exists. Therefore, we considered incorporating a holographic technology, an ideal three-dimensional (3D) display technology, into an AR HMD system. A few studies on holographic HMDs have had technical problems, and they have faults in size and weight. This paper proposes a compact holographic AR HMD system with the purpose of enabling an ideal 3D AR HMD system which can correctly reconstruct the image at any depth. In this paper, a Fourier transform optical system (FTOS) was implemented using only one lens in order to achieve a compact and lightweight structure, and a compact holographic AR HMD system was constructed. The experimental results showed that the proposed system can reconstruct sharp images at the correct depth for a wide depth range. This study enabled an ideal 3D AR HMD system that enables simultaneous viewing of both the real target object and the reconstructed image without feeling visual fatigue.

Rational proofs, introduced by Azar and Micali (STOC 2012), are a variant of interactive proofs in which the prover is rational, and may deviate from the protocol for increasing his reward. Guo et al. (ITCS 2014) demonstrated that rational proofs are relevant to delegation of computation. By restricting the prover to be computationally bounded, they presented a one-round delegation scheme with sublinear verification for functions computable by log-space uniform circuits with logarithmic depth. In this work, we study rational proofs in which the verifier is also rational, and may deviate from the protocol for decreasing the prover's reward. We construct a three-message delegation scheme with sublinear verification for functions computable by log-space uniform circuits with polylogarithmic depth in the random oracle model.