Array antenna technology for wireless systems is highly integrated for demands such as multi-functionality and high-performance. This paper details recent technologies in Japan in design techniques based on computational electromagnetics, antenna hardware techniques in the millimeter-wave band, array signal processing to add adaptive functions, and measurement methods to support design techniques, for array antennas for future wireless systems. Prospects of these four technologies are also described.

Efficient use of heterogeneous wireless access networks is necessary to maximize the capacity of the 5G mobile communications system. The wireless local area networks (WLANs) are considered to be one of the key wireless access networks because of the proliferation of WLAN-capable mobile devices. However, throughput starvation can occur due to the well-known exposed/hidden terminal problem in carrier sense multiple access with collision avoidance (CSMA/CA) based channel access mechanism, and this problem is a critical issue with wireless LAN systems. This paper proposes two novel schemes to identify starved access points (APs) and user equipments (UEs) which throughputs are relatively low. One scheme identifies starved APs by observing the transmission delay of beacon signals periodically transmitted by APs. The other identifies starved UEs by using the miscaptured beacon signals ratio at UEs. Numerous computer simulations verify that that the schemes can identify starved APs and UEs having quite low throughput and are superior to the conventional graph-based identification scheme. In addition, AP and UE management with the proposed schemes has the potential to improve system throughput and reduce the number of low throughput UEs.

In this paper, the effect of the tilt angle of return stroke channel and the stratified lossy ground on the lightning-induced voltages on the overhead lines are studied using the modified transmission-line model with linear current decay with height (MTLL). The results show that the lightning-induced voltages from oblique discharge channel are larger than those from the vertical discharge channel, and the peak values of the induced voltages will increase with increasing the tilt angle. When the ground is horizontally stratified, the peak of the induced voltages will increase with increasing the conductivity of the lower layer at different distances. When the upper ground conductivity increases, the voltage peak values will decrease if the overhead line is nearby the lightning strike point and increase if the overhead line is far from the lightning strike point. Moreover, the induced voltages are mainly affected by the conductivity of the lower layer soil when the conductivity of the upper layer ground is smaller than that of the lower layer ground at far distances. When the ground is vertically stratified, the induced voltages are mainly affected by the conductivity of the ground near the strike point when the overhead line and the strike point are located above the same medium; if the overhead line and the strike point are located above different mediums, both of the conductivities of the vertically stratified ground will influence the peak of the induced voltages and the conductivity of the ground which is far from the strike point has much more impact on induced voltages.

In the topologies for interconnected nodes, it is desirable to have a low degree and a small diameter. For the same number of nodes, a dual-cube topology has almost half the degree compared to a hypercube while increasing the diameter by just one. Hence, it is a promising topology for interconnection networks of massively parallel systems. We propose here a stochastic fault-tolerant routing algorithm to find a non-faulty path from a source node to a destination node in a dual-cube.

This paper presents FIR digital filters based on stochastic/binary hybrid computation with reduced hardware complexity and high computational accuracy. Recently, some attempts have been made to apply stochastic computation to realization of digital filters. Such realization methods lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic digital filters suffer from lower computational accuracy than the digital filters based on binary computation because of the random error fluctuations that are generated in stochastic bit streams, stochastic multipliers, and stochastic adders. This becomes a serious problem in the case of FIR filter realizations compared with the IIR counterparts because FIR filters usually require larger number of multiplications and additions than IIR filters. To improve the computational accuracy, this paper presents a stochastic/binary hybrid realization, where multipliers are realized using stochastic computation but adders are realized using binary computation. In addition, a coefficient-scaling technique is proposed to further improve the computational accuracy of stochastic FIR filters. Furthermore, the transposed structure is applied to the FIR filter realization, leading to reduction of hardware complexity. Evaluation results demonstrate that our method achieves at most 40dB improvement in minimum stopband attenuation compared with the conventional pure stochastic design.

This letter considers a backscatter assisted wireless powered communication network (BAWPCN) with non-orthogonal multiple access (NOMA). This model consists of a hybrid access point (HAP) and multiple users which can work in either backscatter or harvest-then-transmit (HTT) protocol. To fully exploit time for information transmission, the users working in the backscatter protocol are scheduled to reflect modulated signals during the first phase of the HTT protocol which is dedicated for energy transfer. During the second phase, all users working in the HTT protocol transmit information to the HAP simultaneously since NOMA is adopted. Considering both short-term and long-term optimization problems to maximize the system throughput, the optimal resource allocation policies are obtained. Simulation results show that the proposed model can significantly improve the system performance.

Inter-switch networks for HPC systems and data-centers can be improved by applying random shortcut topologies with a reduced number of hops. With minimal routing in such networks; however, deadlock-freedom is not guaranteed. Multiple Virtual Channels (VCs) are efficiently used to avoid this problem. However, previous works do not provide good trade-offs between the number of required VCs and the time and memory complexities of an algorithm. In this work, a novel and fast algorithm, named ACRO, is proposed to endorse the arbitrary routing functions with deadlock-freedom, as well as consuming a small number of VCs. A heuristic approach to reduce VCs is achieved with a hash table, which improves the scalability of the algorithm compared with our previous work. Moreover, experimental results show that ACRO can reduce the average number of VCs by up to 63% when compared with a conventional algorithm that has the same time complexity. Furthermore, ACRO reduces the time complexity by a factor of O(|N|⋅log|N|), when compared with another conventional algorithm that requires almost the same number of VCs.

The Möbius cube is a variant of the hypercube. Its advantage is that it can connect the same number of nodes as a hypercube but with almost half the diameter of the hypercube. We propose an algorithm to solve the node-to-node disjoint paths problem in n-Möbius cubes in polynomial-order time of n. We provide a proof of correctness of the algorithm and estimate that the time complexity is O(n2) and the maximum path length is 3n-5.

For some applications, it has been known that stochastic computing (SC) has many potential advantages compared with conventional computation on binary radix encoding. Thus, there has been proposed many design methodologies to realize SCs. Recently, a general design method to realize SC operations by designing Boolean circuits (functions) has been proposed. As a central part of the method, we need to design a logic circuit such that its output becomes 1 with a certain desired probability with respect to random inputs. Also, to realize an SC arithmetic operation with a constant value, in some situations we need to prepare a random bit-stream that becomes 1 with a desired probability from a set of predetermined physical random sources. We call such a bit-stream as a stochastic number (SN). We can utilize the above-mentioned previous method to prepare stochastic numbers by designing Boolean circuits. The method assumes all the random sources become 1 with the same probability 1/2. In this paper, we investigate a different framework where we can prepare different probabilities of each stochastic number in the physical random sources. Then, this paper presents the necessary and sufficient condition of given random inputs in order to produce a stochastic number with a given specified precision. Based on the condition, we can propose a method to generate a stochastic number by using the minimum number of random inputs. Indeed our method uses much less number of inputs than the previous method, and our preliminary experiment shows that the generated circuits by our method also tend to be smaller than the ones by the previous method.

This paper discusses key technologies specific for fifth generation (5G) cellular systems which are expected to connect internet of things (IoT) based vertical sectors. Because services for 5G will be expanded drastically, from information transfer services to mission critical and massive connection IoT connection services for vertical sectors, and requirement for cellular systems becomes quite different compared to that of fourth generation (4G) systems, after explanation for the service and technical trends for 5G, key wireless access technologies will be discussed, especially, from the view point of what is new and how import. In addition to the introduction of new technologies for wireless access, flexibility of networking is also discussed because it can cope with QoS support services, especially to cope with end-to-end latency constraint conditions. Therefore, this paper also discuss flexible network configuration using mobile edge computing (MEC) based on software defined network (SDN) and network slicing.

This paper presents a high-throughput sliding block Viterbi decoder for IEEE 802.11ac systems. A 64-state bidirectional sliding block Viterbi method is proposed to meet the speed requirement of the system. The decoder throughput goes up to 640Mbps, which can be further increased by adding the block parallelism. Moreover, a modified add-compare-select (ACS) unit is designed to enhance the working frequency. The modified ACS unit obtains nearly 26% speed-up, compared to the conventional ACS unit. However, the area overhead and power dissipation are almost the same. The decoder is designed in a SMIC 0.13µm technology, and it occupies 1.96mm2 core area and 105mW power consumption with an energy efficiency of 0.1641nJ/bit with a 1.2V voltage supply.

With the availability of virtualization extension in mobile processors, e.g. ARM Cortex A-15, multiple virtual execution domains are efficiently supported in a mobile platform. Each execution domain requires high-performance graphics services for full-featured user interfaces such as smooth scrolling, background image blurring, and 3D images. However, graphics service is hard to be virtualized because multiple service components (e.g. ION and Fence) are involved. Moreover, the complexity of Graphical Processing Unit (GPU) device driver also makes harder virtualizing graphics service. In this paper, we propose a technique to virtualize the graphics architecture of Android mobile platform in KVM/ARM environment. The Android graphics architecture relies on underlying Linux kernel services such as the frame buffer memory allocator ION, the buffer synchronization service Fence, GPU device driver, and the display synchronization service VSync. These kernel services are provided as device files in Linux kernel. Our approach is to para-virtualize these device files based on a split device driver model. A major challenge is to translate guest-view of information into host-view of information, e.g. memory address translation, file descriptor management, and GPU Memory Management Unit (MMU) manipulation. The experimental results show that the proposed graphics virtualization technique achieved almost 84%-100% performance of native applications.

In this letter, we focus on a system where N sources send n ≤ N different packets to one destination, through M ≥ N relays. Each relay employs random linear network coding to encode the packets it received by randomly choosing coefficients in a finite field Fq, then forwards it to the destination. Owing to the inherent errorprone nature of erasure channels, data packets received by the relay and the destination nodes may not be correct. We analyze the optimal throughput with respect to n, given a series of parameters and derive the upper and lower bounds of throughput performance. We also analyze the impact of the number of relays and the erasure probability on the throughput performance. Simulation results are well matched with the theoretical analysis.

Object detection is at the heart of nearly all the computer vision systems. Standard off-the-shelf embedded processors are hard to meet the trade-offs among performance, power consumption and flexibility required by object detection applications. Therefore, this paper presents an Application Specific Instruction set Processor (ASIP) for object detection using AdaBoost-based learning algorithm with Haar-like features as weak classifiers. Algorithm optimizations are employed to reduce memory bandwidth requirements without losing reliability. In the proposed ASIP, Single Instruction Multiple Data (SIMD) architecture is adopted for fully exploiting data-level parallelism inherent to the target algorithm. With adding pipeline stages, application-specific hardware components and custom instructions, the AdaBoost algorithm is accelerated by a factor of 13.7x compared to the optimized pure software implementation. Compared with ARM946 and TMS320C64+, our ASIP shows 32x and 7x better throughput, 10x and 224x better area efficiency, 6.8x and 18.8x better power efficiency, respectively. Furthermore, compared to hard-wired designs, evaluation results show an advantage of the proposed architecture in terms of chip area efficiency while maintain a reliable performance and achieve real-time object detection at 32fps on VGA video.

During the development of a human embryo, the position of eyes moves medially and caudally in the viscerocranium. A statistical model of this process can play an important role in embryology by facilitating qualitative analyses of change. This paper proposes an algorithm to construct a spatiotemporal statistical model for the eyeballs of a human embryo. The proposed modeling algorithm builds a statistical model of the spatial coordinates of the eyeballs independently for each Carnegie stage (CS) by using principal component analysis (PCA). In the process, a q-Gaussian distribution with a model selection scheme based on the Aaike information criterion is used to handle a non-Gaussian distribution with a small sample size. Subsequently, it seamlessly interpolates the statistical models of neighboring CSs, and we present 10 interpolation methods. We also propose an estimation algorithm for the CS using our spatiotemporal statistical model. A set of images of eyeballs in human embryos from the Kyoto Collection was used to train the model and assess its performance. The modeling results suggested that information geometry-based interpolation under the assumption of a q-Gaussian distribution is the best modeling method. The average error in CS estimation was 0.409. We proposed an algorithm to construct a spatiotemporal statistical model of the eyeballs of a human embryo and tested its performance using the Kyoto Collection.

Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

Linked Open Data (LOD) at Schema-Level and knowledge described in Chinese is an important part of the LOD project. Previous work generally ignored the rules of word-order sensitivity and polysemy in Chinese or could not deal with the out-of-vocabulary (OOV) mapping task. There is still no efficient system for large-scale Chinese ontology mapping. In order to solve the problem, this study proposes a novel TongYiCiCiLin (TYCCL) and Sequence Alignment-based Chinese Ontology Mapping model, which is called TongSACOM, to evaluate Chinese concept similarity in LOD environment. Firstly, an improved TYCCL-based similarity algorithm is proposed to compute the similarity between atomic Chinese concepts that have been included in TYCCL. Secondly, a global sequence-alignment and improved TYCCL-based combined algorithm is proposed to evaluate the similarity between Chinese OOV. Finally, comparing the TongSACOM to other typical similarity computing algorithms, and the results prove that it has higher overall performance and usability. This study may have important practical significance for promoting Chinese knowledge sharing, reusing, interoperation and it can be widely applied in the related area of Chinese information processing.

This paper proposes a formal approach of verifying ubiquitous computing application scenarios. Ubiquitous computing application scenarios assume that there are a lot of devices and physical things with computation and communication capabilities, which are called smart objects, and these are interacted with each other. Each of these interactions among smart objects is called “federation”, and these federations form a ubiquitous computing application scenario. Previously, Yuzuru Tanaka proposed “a proximity-based federation model among smart objects”, which is intended for liberating ubiquitous computing from stereotyped application scenarios. However, there are still challenges to establish the verification method of this model. This paper proposes a verification method of this model through model checking. Model checking is one of the most popular formal verification approach and it is often used in various fields of industry. Model checking is conducted using a Kripke structure which is a formal state transition model. We introduce a context catalytic reaction network (CCRN) to handle this federation model as a formal state transition model. We also give an algorithm to transform a CCRN into a Kripke structure and we conduct a case study of ubiquitous computing scenario verification, using this algorithm and the model checking. Finally, we discuss the advantages of our formal approach by showing the difficulties of our target problem experimentally.

This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fsrms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

This letter introduces a new model for backscatter assisted wireless powered communication networks (BAWPCNs) that include a hybrid access point (HAP) and multiple backscatter communication (BackCom) and traditional wireless powered communication network (WPCN) users. To make full use of time to transmit information, both backscatter and harvest-then-transmit (HTT) modes are employed. In the proposed model, during the first time slot dedicated for energy transfer in traditional WPCNs, the traditional WPCN users harvest energy radiated by the HAP, and simultaneously the BackCom users reflect modulated signals to the HAP. The traditional WPCN users are scheduled during the remaining time slots via time division multiple access (TMDA). The optimal time allocation policies for the half-duplex (HD) and full-duplex (FD) BAWPCNs are obtained to maximize the system throughput. The tradeoff between backscatter and HTT modes is analyzed. Simulation results demonstrate the superiority of the proposed model.