A static timing analysis (STA) tool for a 28nm atom-switch FPGA (AS-FPGA) is introduced to validate the signal delay of an application circuit before implementation. High accuracy of the STA tool is confirmed by implementing a practical application circuit on the 28nm AS-FPGA. Moreover, dramatic improvement of delay and power is demonstrated in comparison with a previous 40nm AS-FPGA.

In this work, the bias polarity dependent resistive switching behaviors in Cu/Si3N4/p+ Si RRAM memory cell have been closely studied. Different switching characteristics in both unipolar and bipolar modes after the positive forming are investigated. The bipolar switching did not need a forming process and showed better characteristics including endurance cycling, uniformity of switching parameters, and on/off resistance ratio. Also, the resistive switching characteristics by both positive and negative forming switching are compared. It has been confirmed that both unipolar and bipolar modes after the negative forming exhibits inferior resistive switching performances due to high forming voltage and current.

In this work, resistive switching random-access memory (RRAM) devices having a structure of metal/Si$_{3}$N$_{4}$/Si with different top electrode metals were fabricated to investigate the changes in switching and conduction mechanisms depending on electrode metals. It is shown that the metal workfunction is not strongly related with either high-resistance state (HRS) and forming voltage. Top electrodes (TEs) of Al, Cu, and Ni show both bipolar and unipolar switching characteristics. The changes of resistances in these devices can be explained by the different defect arrangements in the switching layer (SL). Among the devices with different TE metals, one with Ag electrode does not show unipolar switching unlike the others. The conducting filaments of Ag-electrode device in the low-resistance state (LRS) demonstrated metallic behaviors in the temperature-controlled experiments, which supports that Ag substantially participates in the conduction as a filament source. Moreover, the difference in switching speed is identified depending on TE metals.

This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25 kΩ to 65 kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

A novel 3D RRAM concept using a stackable multi-layer 1TXR memory cell structure is proposed. The access transistor is fabricated in silicon, which has excellent affinity to the standard CMOS process. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Further, a corresponding operation algorithm is put forward, which can inhibit effectively mis-write and mis-read caused by sneaking current and reduce power consumption.