The decoders, which improve the error-correction performance by finding and correcting the error bits caused by channel noise, are a hotspot for polar codes. In this paper, we present a threshold based D-SCFlip (TD-SCFlip) decoder with two improvements based on the D-SCFlip decoder. First, we propose the LLR fidelity criterion to define the LLR threshold and investigate confidence probability to calculate the LLR threshold indirectly. The information bits whose LLR values are smaller than the LLR threshold will be excluded from the range of candidate bits, which reduces the complexity of constructing the flip-bits list without the loss of error-correction performance. Second, we improve the calculation method for flip-bits metric with two perturbation parameters, which locates the channel-induced error bits faster, thus improving the error-correction performance. Then, TD-SCFlip-ω decoder is also proposed, which is limited to correcting up to ω bits in each extra decoding attempt. Simulation results show that the TD-SCFlip decoding is slightly better than the D-SCFlip decoding in terms of error-correction performance and decoding complexity, while the error-correction performance of TD-SCFlip-ω decoding is comparable to that of D-SCFlip-ω decoding but with lower decoding complexity.

An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.

The authors report on a 22-Gbit/s static decision IC fabricated with 0. 12-µm GaAs MESFETs. The key to attaining high-speed decision IC is the employment of a novel high-speed D-type flip-flop (D-FF). The D-FF succeeds in faster operation through the simplification of the circuitry and the reduction of the transition time of the output voltages.

In order to develop high-speed ICs, it is important to clarify the relationship between circuit speed and device parameters. An analytical expression for circuit performance is effective for this purpose. This paper describes an analytical toggle frequency expression for Source-Coupled FET Logic (SCFL) frequency dividers. The proposed equation is expressed as the sum of the product of sensitivity coefficients of FET parameters and time constants which are extracted through a small signal transfer function analysis. These sensitivity coefficients are extracted using SPICE simulations. The equation is a simple formula with only five coefficients, which is much smaller than conventional sensitivity analyses. Furthermore, the accuracy of the proposed equation is improved compared to an analytical method based on the small signal transfer function which we previously proposed. The equation can be easily extended to consider interconnection delay time. The calculated maximum toggle frequencies using the equation show good agreement with SPICE simulations and experimental results for a wide gate-length variation range of 0. 12-µm to 0. 24-µm GaAs MESFETs. By re-extraction of another set of sensitivity coefficients, the proposed equation can be widely applied to shorter gate-length GaAs MESFETs and other FET devices such as HEMT devices. The expression clearly shows the relationship between the circuit performance and intrinsic FET parameters. According to the equation, the key parameters for high-speed circuit operation are high transconductance with a low drain conductance, and a low gate-drain capacitance. The equation can be used as a criterion for the optimization of the FET structure to realize high speed circuit performance.

GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

This letter reports a high-sensitivity GaAs decision IC for ultra-high-speed optical transmission systems. The IC was designed using LSCFL (Low-power Source Coupled FET Logic) and fabricated with 0.2-µm-gate-length MESFETs with a cut-off frequency of 50GHz. The input voltage sensitivity was 35mV at 10Gbit/s. This is the highest sensitivity ever reported for a MESFET decision IC.