Ultrasonic imaging is useful in seabed or lakebed observations. We can roughly estimate the sea depth by hearing the echo generated by the boundary of water and rocks or sand. However, the estimation quality is usually not sufficient to draw seabed landscape since the echo signal includes serious distortion caused by autointerference. This paper proposes a novel method to visualize the shape of distant boundaries, such as the seawater-rock/sand boundary, based on the complex-valued Markov random field (CMRF) model. Our method realizes adaptive compensation of distortion without changing the global features in the measurement data, and obtains higher-quality landscape with less computational cost than conventional methods.

In this paper, we design and analyze some new and practical (selectively) convertible undeniable signature (SCUS) schemes in both random oracle and standard model, which enjoy several merits over existing schemes in the literature. In particular, we design the first practical RSA-based SCUS schemes secure in the standard model. On the path, we also introduce two moduli RSA assumptions, including the strong twin RSA assumption, which is the RSA symmetry of the strong twin Diffie-Hellman assumption (Eurocrypt'08).

In this paper, we propose a rapid model adaptation technique for emotional speech recognition which enables us to extract paralinguistic information as well as linguistic information contained in speech signals. This technique is based on style estimation and style adaptation using a multiple-regression HMM (MRHMM). In the MRHMM, the mean parameters of the output probability density function are controlled by a low-dimensional parameter vector, called a style vector, which corresponds to a set of the explanatory variables of the multiple regression. The recognition process consists of two stages. In the first stage, the style vector that represents the emotional expression category and the intensity of its expressiveness for the input speech is estimated on a sentence-by-sentence basis. Next, the acoustic models are adapted using the estimated style vector, and then standard HMM-based speech recognition is performed in the second stage. We assess the performance of the proposed technique in the recognition of simulated emotional speech uttered by both professional narrators and non-professional speakers.

Dramatic gains in channel capacity can be achieved in the closed-loop MIMO system under the assumption that the base station (BS) can acquire the downlink channel state information (CSI) accurately. However, transmitting CSI with high precision is a heavy burden that wastes a lot of uplink bandwidth, while transmitting CSI within a limited bandwidth leads to the degradation of system performance. To address this problem, we propose a zero-overhead downlink CSI feedback scheme based on the hybrid pilot structure. The downlink CSI is contained in the hybrid pilots at mobile terminal (MT) side, fed back to BS via the uplink pilot channel, and recovered from hybrid pilot at BS side. Meanwhile the uplink channel is estimated based on the hybrid pilot at BS side. Since transmitting the hybrid pilots occupies the same bandwidth as transmitting traditional code division multiplexing based uplink pilots, no extra uplink channel bandwidth is occupied. Therefore, the overhead for downlink CSI feedback is zero. Moreover, the hybrid pilots are formed at MT side by superposing the received analog downlink pilots directly on the uplink pilots. Thus the downlink CSI estimation process is unnecessary at MT side, and MT's complexity can be reduced. Numerical Simulations prove that, the proposed downlink CSI feedback has the higher precision than the traditional feedback schemes while the overhead for downlink CSI feedback is zero.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

The NTRU cryptosystem is a public key system based on lattice problems. While its theoretical security has been well studied, little effort has been made to analyze its security against implementation attacks including power analysis attacks. In this paper, we show that a typical software implementation of NTRU is vulnerable to the simple power analysis and the correlation power analysis including a second-order power attack. We also present novel countermeasures to prevent these attacks, and perform experiments to estimate the performance overheads of our countermeasures. According to our experimental results, the overheads in required memory and execution time are only 8.17% and 9.56%, respectively, over a Tmote Sky equipped with an MSP430 processor.

Conventional efficient key recovery attacks against Wired Equivalent Privacy (WEP) require specific initialization vectors or specific packets. Since it takes much time to collect the packets sufficiently, any active attack should be performed. An Intrusion Detection System (IDS), however, will be able to prevent the attack. Since the attack logs are stored at the servers, it is possible to prevent such an attack. This paper proposes an algorithm for recovering a 104-bit WEP key from any IP packets in a realistic environment. This attack needs about 36,500 packets with a success probability 0.5, and the complexity of our attack is equivalent to about 220 computations of the RC4 key setups. Since our attack is passive, it is difficult for both WEP users and administrators to detect our attack.

Recently, proportionate adaptive algorithms have been proposed to speed up convergence in the identification of sparse impulse response. Although they can improve convergence for sparse impulse responses, the steady-state misalignment is limited by the constant step-size parameter. In this article, based on the principle of least perturbation, we first present a derivation of normalized version of proportionate algorithms. Then by taking the disturbance signal into account, we propose a variable step-size proportionate NLMS algorithm to combine the benefits of both variable step-size algorithms and proportionate algorithms. The proposed approach can achieve fast convergence with a large step size when the identification error is large, and then considerably decrease the steady-state misalignment with a small step size after the adaptive filter reaches a certain degree of convergence. Simulation results verify the effectiveness of the proposed approach.

This letter proposes the Inference Algorithm through Effective Slot Allocation (ESA-IA). In ESA-IA, the tags which match the prefix of the reader's request-respond in the corresponding slot; the group of tags with an even number of 1's responds in slot 0, while the group with an odd number of 1's responds in slot 1. The proposed algorithm infers '00' and '11' if there are two collided bits in slot 0, while inferring '01' and '10' if there are two collided bits in slot 1. The ESA-IA decreases the time consumption for tag identification by reducing the overall number of queries.

Due to the importance of maintaining the orthogonality among subcarriers, the estimation of carrier frequency offset (CFO) is a crucial issue in orthogonal frequency division multiplexing (OFDM) systems. The CFO estimation becomes complicated in OFDM direct-conversion receivers (DCRs), where additional analog impairments such as I/Q imbalance and time-varying DC offset (TV-DCO) exist. In this paper, we propose a novel joint estimation method for CFO and I/Q imbalance in the presence of TV-DCO. By using the linear property of the TV-DCO and employing a periodic pilot sequence, the desired estimates can be obtained in closed-form. Simulation results confirm the validity of the proposed method.

Since scan testing is not based on the function of the circuit, but rather the structure, it is considered to be both a form of over testing and under testing. Moreover, it is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a fault-dependent test generation method to detect specified fault models completely and to increase defect coverage as much as possible under the test length constraint. We present experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and to show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

This paper addresses the relationships between diversity techniques and channel coding rates for OFDM systems. While a low channel coding rates is required if cyclic delay diversity is applied, the necessity of a low channel coding rate is alleviated with space time block coding.

This paper introduces a new computational problem on a two-dimensional vector space, called the vector decomposition problem (VDP), which is mainly defined for designing cryptosystems using pairings on elliptic curves. We first show a relation between the VDP and the computational Diffie-Hellman problem (CDH). Specifically, we present a sufficient condition for the VDP on a two-dimensional vector space to be at least as hard as the CDH on a one-dimensional subspace. We also present a sufficient condition for the VDP with a fixed basis to have a trapdoor. We then give an example of vector spaces which satisfy both sufficient conditions and on which the CDH is assumed to be hard in previous work. In this sense, the intractability of the VDP is a reasonable assumption as that of the CDH.

Lots of revocable group signature schemes have been proposed so far. In one type of revocable schemes, signing and/or verifying algorithms have O(N) or O(R) complexity, where N is the group size and R is the number of revoked members. On the other hand, in Camenisch-Lysyanskaya scheme and the followers, signing and verifying algorithms have O(1) complexity. However, before signing, the updates of the secret key are required. The complexity is O(R) in the worst case. In this paper, we propose a revocable scheme with signing and verifying of O(1) complexity, where any update of secret key is not required. The compensation is the long public key of O(N). In addition, we extend it to the scheme with O()-size public key, where signing and verifying have constant extra costs.

This paper proposes a compact hardware (H/W) implementation for the MISTY1 block cipher, which is one of the ISO/IEC 18033-3 standard encryption algorithms. In designing the compact H/W, we focused on optimizing the implementation of FO/FI/FL functions, which are the main components of MISTY1. For this optimization, we propose three new methods; reducing temporary registers for the FO function, shortening the critical path for the FI function, and merging the FL/FL-1 functions. According to our logic synthesis on a 0.18-µm CMOS standard cell library based on our proposed methods, the gate size is 3.4 Kgates, which is the smallest as far as we know.

This paper presents a numerical approach to the time-domain analysis of N-branch-line couplers. The approach is based on the modified central difference (MCD) method combined with internal boundary treatments, which consist of the time-domain scattering matrix for the three-port junction discontinuity. The behavior of the signal propagation including multiple reflections on the N-branch-line coupler with and without line loss is analyzed and demonstrated in the time domain. Additionally, the S-parameters obtained from Gaussian pulse responses of the N-branch-line directional couplers are shown. The simulated results are in good agreement with those of the commercial simulator.

As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.

In 2007, Ding et al. proposed an attractive scheme, which is called the -Invertible Cycles (IC) scheme. IC is one of the most efficient multivariate public-key cryptosystems (MPKC); these schemes would be suitable for using under limited computational resources. In 2008, an efficient attack against IC using Grobner basis algorithms was proposed by Fouque et al. However, they only estimated the complexity of their attack based on their experimental results. On the other hand, Patarin had proposed an efficient attack against some multivariate public-key cryptosystems. We call this attack Patarin's attack. The complexity of Patarin's attack can be estimated by finding relations corresponding to each scheme. In this paper, we propose an another practical attack against the IC encryption/signature scheme. We estimate the complexity of our attack (not experimentally) by adapting Patarin's attack. The attack can be also applied to the IC- scheme. Moreover, we show some experimental results of a practical attack against the IC/IC- schemes. This is the first implementation of both our proposed attack and an attack based on Grobner basis algorithm for the even case, that is, a parameter is even.

A simple closed-form approximation for the outage capacity of Transmit Antenna Selection/Maximal-Ratio Combining (TAS/MRC) systems over independent and identically distributed (i.i.d) Nakagami-m fading channels is derived while the fading index is a positive integer. When the Nakagami-m fading index is not an integer, the approximate outage capacity is derived as a single infinite series of Gamma function. Computer simulations verify the accuracy of the approximate results.

This paper proposes an improved method that uses a K-means method to effectively reduce the ringing artifacts in a color moving picture. To apply this improved K-method, we set the number of groups for the process to two (K=2) in the three dimensional R, G, B color space. We then improved the R, G, B color value of all of the pixels by moving the current R, G, B color value of each pixel to calculated center values, which reduced the ringing artifacts. The results were verified by calculating the overshoot and the slope of the light luminance around the edges of test images that had been processed by the new algorithm. We then compared the calculated results with the overshoot and slope of the light luminance of the unprocessed image.