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11841-11860hit(16314hit)

  • A 600-700 GHz Resonant Distributed Junction for a Fixed-Tuned Waveguide Receiver

    Teruhiko MATSUNAGA  Cheuk-yu Edward TONG  Raymond BLUNDELL  Takashi NOGUCHI  

     
    PAPER-Mixers and Detectors

      Vol:
    E85-C No:3
      Page(s):
    738-741

    The non-linear quasiparticle tunnel current flowing in a distributed superconductor-insulator-superconductor (SIS) transmission line resonator has been exploited in a low-noise heterodyne fixed-tuned waveguide receiver in the 600-700 GHz band. The mixer employs two half-wave or full-wave distributed SIS long junctions connected in series. These devices have been fabricated with optical lithography. At 654 GHz, a Y-factor of 1.79 has been recorded, corresponding to a double-side-band (DSB) receiver noise temperature of 198 K at an IF of 3 GHz.

  • Low-Distortion Waveform Synthesis with Josephson Junction Arrays

    Samuel P. BENZ  Fred L. WALLS  Paul D. DRESSELHAUS  Charles J. BURROUGHS  

     
    INVITED PAPER-Digital Devices and Their Applications

      Vol:
    E85-C No:3
      Page(s):
    608-611

    We present measurements of kilohertz and megahertz sine waves synthesized using a Josephson arbitrary waveform synthesizer. A 4.8 kHz sine wave synthesized using an ac-coupled bias technique is shown to have a stable 121 mV peak voltage and harmonic distortion 101 dB below the fundamental (-101 dBc (carrier)). We also present results of our first phase-noise measurement. A 5.0 MHz sine wave was found to have distortion 33 dB lower than the same signal synthesized using a semiconductor digital code generator. The white-noise floor of the Josephson synthesized signal is -132 dBc/Hz and is limited by the noise floor of the preamplifier.

  • Low Spurious Frequency Setting Algorithm for a Triple Tuned Type PLL Synthesizer Driven by a DDS

    Ken'ichi TAJIMA  Yoshihiko IMAI  Yousuke KANAGAWA  Kenji ITOH  Yoji ISOTA  Osami ISHIDA  

     
    LETTER

      Vol:
    E85-C No:3
      Page(s):
    595-598

    This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

  • Capacity Maximizing Linear Space-Time Codes

    Robert W. HEATH, Jr.   Arogyaswami J. PAULRAJ  

     
    PAPER-Digital Transmission

      Vol:
    E85-C No:3
      Page(s):
    428-435

    Spatial multiplexing, or BLAST, is a signaling technique for multiple-input multiple-output (MIMO) channels in which multiple independent data streams are transmitted in parallel in space. The independence between streams, unfortunately, limits the diversity advantage. In this paper we present a space-time code design, using the linear dispersion code framework, for MIMO Rayleigh fading channels. Our design provides codes that have the same ergodic capacity performance as spatial multiplexing but allows for improved diversity advantage. We present a technique for finding good codes based on successive projection. Monte Carlo simulations illustrate performance improvements over spatial multiplexing in terms of bit error probability.

  • HTS Quasi-Particle Injection Devices for Interfaces between SFQ and CMOS Circuits

    Hidehiro SHIGA  Yoichi OKABE  

     
    PAPER-Digital Devices and Their Applications

      Vol:
    E85-C No:3
      Page(s):
    650-653

    We have fabricated a prototype of interface devices between SFQ and CMOS circuits using HTS quasi-particle injection devices. By the injection of quasi-particles, the bridge area becomes resistive and high voltage appears at the drain electrode. As a test of device operation, we applied the signal of a function generator to the gate electrode and observed that the device successfully repeated on/off operation. We also succeeded in explaining the device characteristics by considering the thermal effects.

  • Iterative Demodulation and Channel Estimation of Orthogonal Signaling Formats in Asynchronous DS-CDMA Systems

    Erik G. STROM  Scott L. MILLER  

     
    PAPER-Digital Transmission

      Vol:
    E85-C No:3
      Page(s):
    442-451

    Iterative schemes for demodulating M-ary orthogonal signaling formats in direct-sequence code-division multiple access (DS-CDMA) systems are proposed and compared with the standard noncoherent matched filter receiver. Interference cancellation, i.e., (approximative) removal of the multiple access interference (MAI) by means of subtraction is studied. The considered system is similar to the uplink (reverse link) of an IS-95 system. Hence, the received signals from the concurrent users are asynchronous, and no pilot signals are available for channel estimation. A decision-directed algorithm is proposed for estimating the time-varying complex channel gains of a multipath channel. The receivers are evaluated on Rayleigh-fading channels and are shown to provide large capacity gains compared with the conventional receiver.

  • Turbo Equalization of GMSK Signals Using Noncoherent Frequency Detection

    Tomoya OKADA  Yasunori IWANAMI  

     
    PAPER-Digital Transmission

      Vol:
    E85-C No:3
      Page(s):
    473-479

    In this paper, we propose a turbo equalization scheme for GMSK signals with frequency detection. Although the channel is AWGN, there exists severe ISI (Inter-Symbol Interference) in the received signal due to the premodulation Gaussian baseband filter in the transmitter as well as the narrowband IF filter in the receiver. We regard these two filters as a real number inner convolutional encoder. The ISI equalizer for this inner encoder and the outer decoder for a RSC (Recursive Systematic Convolutional) code, are connected through a random (de-)interleaver. These inner and outer decoders generate the reliability values in terms of LLR (Log Likelihood Ratio), using MAP or SOVA algorithm with SISO (soft input and soft output). Moreover iterative decoding with the limitation of LLR values are employed between two decoders to achieve a turbo equalization for GMSK frequency detection. Through computer simulations, the proposed system shows the BER=10-5 at Eb/N0=8.8 dB, when we take BT=0.6 (IF filter bandwidth multiplied by symbol duration) with the iteration number of 3. This means 3.1 dB improvement compared with the conventional scheme where the inner ISI equalizer is concatenated with the outer hard decision Viterbi decoder.

  • Flux-Quantum Transitions in a Three-Junction SQUID Controlled by Two RF Signals

    Yoshinao MIZUGAKI  Jian CHEN  Kensuke NAKAJIMA  Tsutomu YAMASHITA  

     
    PAPER-Novel Devices and Device Physics

      Vol:
    E85-C No:3
      Page(s):
    803-808

    We present analytical and numerical results on the flux-quantum transitions in a three-junction superconducting quantum interference device (3J-SQUID) controlled by two RF signals. The 3J-SQUID has two superconducting loops, and the RF signals are magnetically coupled to the loops. Flux-quantum transitions in the 3J-SQUID loops can be controlled by utilizing the phase difference of the two RF signals. Under proper conditions, we can obtain a situation where one flux quantum passes through the 3J-SQUID per one cycle of the RF signals without DC current biasing, which results in a zero-crossing step on the current-voltage characteristics. In this paper, we first explain the operation principle by using a quantum state diagram of a 3J-SQUID. Next, we numerically simulate RF-induced transitions of the quantum states. A zero-crossing step on the current-voltage characteristics is demonstrated. We also investigate dependence of zero-crossing steps upon parameters of the 3J-SQUID and RF signals.

  • Modeling Wide Band Channels Using Orthogonalizations

    Ramon PARRA-MICHEL  Valeri Ya KONTOROVITCH  Aldo Gustavo OROZCO-LUGO  

     
    PAPER-Multipath

      Vol:
    E85-C No:3
      Page(s):
    544-551

    In this article we present the subject of wideband channel modeling and simulation, stressing the method of orthogonalization. We compare the performance of this simulation method using Karhunen-Loeve, Wavelets and other basis over radio channels represented via the Input-Delay Spread Bello Function.

  • Two-Phase Minislot Scheduling Algorithm for HFC QoS Services Provisioning

    Wei-Ming YIN  Chia-Jen WU  Ying-Dar LIN  

     
    PAPER-Fiber-Optic Transmission

      Vol:
    E85-B No:3
      Page(s):
    582-593

    Data-Over-Cable Service Interface Specifications v1.1 (DOCSIS v1.1), developed for data transmissions over Hybrid Fiber Coaxial (HFC) networks, defines five upstream services for supporting per-flow Quality of Services (QoS). The cable modem termination system (CMTS) must periodically grant upstream transmission opportunities to the QoS flows based on their QoS parameters. However, packets may violate QoS requirements when several flows demand the same interval for transmission. This study proposes a two-phase, i.e., the scheduling sequence determination phase and the minislot assignment phase, minislot scheduling algorithm to reduce the QoS violation rate. In the scheduling sequence determination phase, the flow whose packets are most unlikely to violate QoS is scheduled first. Then, in the minislot assignment phase, the scheduler allocates to a flow the available interval where the likelihood of packet violation is minimum. Simulation results demonstrate that our scheduling algorithm can reduce the QoS violation rate by 80-35% over that of the first-come-first-serve-random-selection algorithm. It increases the utilization by 25% as well. The two-phase minislot scheduling algorithm can work within the DOCSIS v1.1 framework.

  • Design of SFQ Circuits and Their Measurement

    Kazunori MIYAHARA  Shuichi NAGASAWA  Haruhiro HASEGAWA  Tatsunori HASHIMOTO  Hideo SUZUKI  Youichi ENOMOTO  

     
    INVITED PAPER-Digital Devices and Their Applications

      Vol:
    E85-C No:3
      Page(s):
    603-607

    In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

  • Optimum Design of a ZCS High Frequency Inverter for Induction Heating

    Hiroyuki OGIWARA  Mutsuo NAKAOKA  

     
    PAPER-Electronic Circuits

      Vol:
    E85-C No:3
      Page(s):
    847-855

    This paper describes the circuit design procedure of the zero-current soft switching (ZCS) high frequency inverter for induction heating uses. Its output power can be regulated from its maximum to minimum by the instantaneous current vector control scheme using phase shift control between switching units at a fixed frequency. In addition, it can be safely operated since no extraordinarily high voltage or current results even at a short-circuit period at the load. Also, its overall efficiency reaches 90%. The detailed load and frequency characteristics of the inverter are elucidated by the computer-aided simulation. Then, the circuit design procedure is presented, and practical numerical examples are obtained according to this procedure which reveal that the inverter is highly practical and the design procedure is effective. The trial inverters yielding 2 kW or 4 kW were actually prepared. The observed values of the voltages and currents of the inverters were found to be in good agreement with the calculated ones. These facts certificate the validity of the proposed design procedure.

  • A New Diagnostic Method Using Probabilistic Temporal Fault Models

    Kazuo HASHIMOTO  Kazunori MATSUMOTO  Norio SHIRATORI  

     
    INVITED PAPER-Artificial Intelligence,Cognitive Science

      Vol:
    E85-D No:3
      Page(s):
    444-454

    This paper introduces a probabilistic modeling of alarm observation delay, and shows a novel method of model-based diagnosis for time series observation. First, a fault model is defined by associating an event tree rooted by each fault hypothesis with probabilistic variables representing temporal delay. The most probable hypothesis is obtained by selecting one whose Akaike information criterion (AIC) is minimal. It is proved by simulation that the AIC-based hypothesis selection achieves a high precision in diagnosis.

  • Microwave Surface Resistance Measurement Sensitivity of HTS Thin Films by Microstripline Resonator at Fundamental and Higher Resonant Modes

    Narayan D. KATARIA  Mukul MISRA  

     
    PAPER-Microwave Devices and Systems

      Vol:
    E85-C No:3
      Page(s):
    696-699

    The measurement sensitivity of microwave surface resistance, Rs, of high temperature superconducting (HTS) thin films using half-wavelength microstrip resonator with copper and HTS ground plane is analyzed for fundamental and higher order modes of the resonator. The estimated sensitivity of Rs-measurement is at least an order of magnitude greater at fundamental resonant frequency compared to when measured using higher order harmonic modes.

  • An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth

    Roberto Y. OMAKI  Gen FUJITA  Takao ONOYE  Isao SHIRAKAWA  

     
    PAPER-Image

      Vol:
    E85-A No:3
      Page(s):
    703-713

    A wavelet based algorithm for scalable video compression is described, with the main focus put on memory bandwidth reduction and efficient VLSI implementation. The proposed algorithm adopts a modified 2-D subband decomposition scheme in conjunction with a partial zerotree search for efficient Embedded Zerotree Wavelet coding. The experiment with the performance of the proposed algorithm in comparison with that of conventional DWT, MPEG-2, and JPEG demonstrates that the image quality of the proposed algorithm is consistently superior to that of JPEG, and our scheme can even outperform MPEG-2 in some cases, although it does not exploit the inter-frame redundancy. In spite of the performance inferiority to the conventional DWT, the proposed algorithm attains significant reduction of DWT memory requirements, enhancing a reasonable balance between implementation cost and image quality.

  • Haar Wavelet Scale Domain Method for Solving the Transient Response of Dispersive Transmission Lines with Nonlinear Loads

    I-Ting CHIANG  Shyh-Kang JENG  

     
    PAPER-Electromagnetic Compatibility(EMC)

      Vol:
    E85-B No:3
      Page(s):
    641-651

    A numerical technique based on Haar wavelets is used for solving transient problems of transmission lines. The approach of our method is to convert the original coupled partial differential equations, the transmission line equations or the telegrapher equations, to a system of ordinary matrix differential equations via Haar wavelets. Then, transient problems of transmission lines can be solved by matrix operations. Numerical examples of homogeneous and dispersive lines, along with both linear and nonlinear loads are verified. In addition, non-sinusoidal signals such as the unit step function and the rectangular pulse for digital applications are included to demonstrate the use of this efficient, easy-to-handle, stable, and versatile method.

  • Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model

    Tadashi SHIBATA  

     
    INVITED PAPER-LSI/Signal Processors

      Vol:
    E85-A No:3
      Page(s):
    600-609

    Despite the enormous power of present-day computers, digital systems cannot respond to real-world events in real time. Biological systems, however, while being built with very slow chemical transistors, are very fast in such tasks like seeing, recognizing, and taking immediate actions. This paper discusses the issue of how we can build real-time intelligent systems directly on silicon. An intelligent VLSI system inspired by a psychological brain model is proposed. The system stores the past experience in the on-chip vast memory and recalls the maximum likelihood event to the current input based on the associative processor architecture. Although the system can be implemented in a CMOS digital technology, we are proposing here to implement the system using circuits operating in the analog/digital-merged decision making principle. Low-level processing is done in the analog domain in a fully parallel manner, which is immediately followed by a binary decision to yield answers in digital formats. Such a scheme would be very advantageous in achieving a high throughput computation under limited memory and computational resources usually encountered in mobile applications. Hardware-friendly algorithms have been developed for real-time image recognition using the associative processor architecture and some experimental results are demonstrated.

  • A Channel Estimation Algorithm for Mobile Communication Systems in a Fading Environment

    Kyoo-Jin HAN  Een-Kee HONG  Sang-Tae KIM  Keum-Chan WHANG  

     
    LETTER-Terrestrial Radio Communications

      Vol:
    E85-B No:3
      Page(s):
    682-685

    In this letter, an algorithm that estimates one of the most important channel parameters, maximum Doppler frequency, fD, is proposed. The algorithm uses phase variations of received pilot signals, which is strongly related with fD in a fading environment. In addition, a phase variation measurement method for binary phase shift keying (BPSK) modulated signals is also proposed and it makes possible to estimate fD from BPSK modulated information signals as well as unmodulated pilot signals. The results show that the proposed algorithm is very simple and shows good performance over wide Doppler frequency range.

  • An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm

    Kengo R. AZEGAMI  Masato INAGI  Atsushi TAKAHASHI  Yoji KAJITANI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E85-A No:3
      Page(s):
    655-663

    In this paper, we propose an improved network-flow based multi-way circuit partitioning algorithm whose objective is to minimize the number of sub-circuits. It iteratively extracts a size-maximal feasible sub-circuit one at a time. In our approach, two devices are applied. One is in the use of an exact min-cut graph, and the other is in the idea of keeping the number of I/O pins of the residual circuit as small as possible after one-time extraction. We implemented our algorithm in C for experiments, and tested it with several industrial cases and MCNC benchmarks. Compared to the known approach, we observed more than 10% reduction in average of the sub-circuit number.

  • Design and Performance of Miniaturized HTS Coplanar Waveguide Bandpass Filters with Highly Packed Meanderlines

    Haruichi KANAYA  Yoko KOGA  Tatsunori SHINTO  Keiji YOSHIDA  

     
    PAPER-Microwave Devices and Systems

      Vol:
    E85-C No:3
      Page(s):
    708-713

    We propose the new and highly accurate design theory of the high Tc superconducting (HTS) miniaturized coplanar waveguide (CPW) bandpass filters (BPFs) with highly packed meanderlines. BPFs are designed using the external quality factor (Qe) and coupling constant (k) (Q-k method). These parameters are estimated from the transmission coefficient obtained by the 2.5-dimensional electromagnetic field simulator. Moreover, the Q-k method is compared with the J-b method (designed using admittance inverter and susceptance slope parameter) presented previously; in this way we confirmed that the Q-k method has higher accuracy than the J-b method. We realized the design of a the highly packed meanderline CPW BPF (5 pole, center frequency = 2 GHz, fractional band width = 15 MHz, ripple = 0.1 dB) in a 3.5 mm 8 mm substrate.

11841-11860hit(16314hit)