A base model should be transmitted first in progressive transmission schemes, and its transmission delay dominates initiation time for rendering. To reduce the initiation time, we restructure the base model to transmit visible vertices and triangles for some specific viewpoints first, and therefore clients can start rendering when parts of model file are received. Simulation results show that only 37.4% - 51.3% of model file are required to start rendering, and hence the initiation time is significantly reduced.

Alamouti proposed a very attractive transmit diversity technique which ensures orthogonality across two transmit antennas. This technique alone, however, offers no coding gain. In this work, powerful binary turbo codes are combined with Alamouti's diversity technique to achieve a coding gain on top of the diversity gain. Performance analysis on the combined scheme is presented and optimum turbo codes with transmit diversity on fading channels are proposed. Simulation results are shown to illustrate the improvement this scheme can offer.

A uniform raised-salicide technology has been investigated using both uniform selective-epitaxial-growth (SEG) silicon and salicide films, to reduce a junction leakage current of shallow source/drain (S/D) regions for high-performance CMOS devices. The uniform SEG-Si film without pits is formed by using a wet process, which is a carbon-free oxide removal only using a dilute hydrofluoric acid (DHF) dipping, prior to the Si-SEG process. After a titanium-salicide formation using a conventional two-step salicide process, this uniform SEG-Si film achieves good S/D junction characteristics. The uniform titanium-salicide film without bowing into a silicon is formed by a smaller Ti/SEG-Si thickness ratio, which results in a low sheet resistance of 5 Ω/sq. without a narrow-line effect. Furthermore, the drive current is maximized by this raised-salicide film using a Ti/SEG-Si thickness ratio of 1.0.

We consider diagnosability of butterfly networks under the comparison approach proposed by Maeng and Malek. Sengupta and Dahbura discussed characterization of diagnosable systems under the comparison approach, and designed a polynomial time algorithm to identify the faulty processors. However, for a general system, it is not algorithmically easy to determine its diagnosability. This paper proposes two comparison schemes for generating syndromes on butterfly networks, and determine the diagnosability of the network.

This letter proposes a design methodology of a capacitor for a switched capacitor filter. The capacitor design method makes the capacitor accurate to the capacitance ratio and insensitive to the process deviation. The SCF designed is used for the PCM CODEC filter and the deviation of the frequency characteristic is below 0.05 dB for a process deviation 0.5 µm in 5 µm CMOS process.

In 1998, Fan and Lei proposed a partially blind signature scheme that could reduce the computation load and the size of the database for electronic cash systems. In this Letter, we show that their scheme could not meet the untraceability property of a blind signature.

This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.

In this letter, we propose high-speed binary to residue converters for moduli 2n, 2n 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 210-1 and 1.73 ns for modulus 210+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 210 1 is 335 µm325 µm.

An English auction is the most familiar type of auctions. Generally, an electronic auction has mainly two entities, the registration manager (RM) who treats the registration of bidders, and the auction manager (AM) who holds auctions. Before starting an auction, a bidder who wants to participate in English auction is registered to RM with her/his information. An electronic English auction protocol should satisfy the following nine properties, (a) Anonymity, (b) Traceability, (c) No framing, (d) Unforgeability, (e) Fairness, (f) Verifiability, (g) Unlinkability among plural auctions, (h) Linkability in an auction, and (i) Efficiency of bidding. Furthermore from the practical point of view we add two properties (j) Easy revocation and (k) One-time registration. A group signature is adapted to an English auction in order to satisfy (a), (b), and (f). However such a direct adoption suffers from the most critical drawback of efficiency in group signatures. In this paper we propose more realistic electronic English auction scheme, which satisfies all of these properties without using a group signature. Notable features of our scheme are: (1) both of bidding and verification of bids are done quite efficiently by introducing a bulletin board, (2) both properties (j) Easy revocation and (k) One-time registration are satisfied.

A new test structure, which has a 0.5 µm line and space polysilicon pattern of which center is aligned on the MOSFET's gate center, is proposed for hot-carrier-induced photoemission analysis in subquarter micron devices. The photoemission-intensity profiles were measured using the photoemission microscope with a liquid N2 cooled CCD imager. We successfully measured a peak position of photoemission intensity from the center of MOSFET's gate with a spatial resolution sufficiently less than 24 nm at the microscope magnification of 1000. The test structure is useful to study the photoemission effects in semiconductor devices.

We propose a subchannel power control scheme in the OFDM system, which transmits data with a variable power level for each subchannel based on the received SNR. The OFDM system, employing the D-QPSK modulation and the proposed subchannel power control with a grouping coefficient equal to 3, gives about 2.3 dB gain in Eb/N0 comparing with the conventional OFDM system, under the two-ray multipath channel with the mean value of the second-ray's attenuation coefficient equal to 0.25, for the required BER equal to 10-5.

In this paper we deal with Voronoi diagram in simply connected complete manifold with non positive curvature, called Hadamard manifold. We prove that a part of the Voronoi diagram can be characterized by hyperbolic Voronoi diagram. Voronoi diagram in simply connected complete manifold is also characterized for a given set of points satisfying a distance condition.

This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.

This paper presents a new decoupling circuit for suppressing radiated emissions due to power plane resonance in multilayer printed circuit boards (PCBs). This circuit is based on transmission line theory, and consists of two decoupling capacitors and one power trace. The two capacitors, one mounted on the power pin of an IC and the other mounted on the common power distribution bus in a board, are connected through the power trace. The characteristic impedance of the trace is much higher than the impedance of the capacitors. In addition, the length of the trace between the capacitors is less than 1/4 the effective wavelength for high frequency (e.g., 1 GHz). Tests we performed on simple PCBs confirm that our decoupling circuit suppresses radiated emissions due to power plane resonance.

A VLSI algorithm for division in GF(2m) with the canonical basis representation is proposed. It is based on the extended Binary GCD algorithm for GF(2m), and performs division through iteration of simple operations, such as shifts and bitwise exclusive-OR operations. A divider in GF(2m) based on the algorithm has a linear array structure with a bit-slice feature and carries out division in 2m clock cycles. The amount of hardware of the divider is proportional to m and the depth is a constant independent of m.

In interconnection networks, deadlock recovery has been studied in routing strategy. The routing strategy for the deadlock recovery is intended to optimize the routing performance when deadlocks do not occur. On the other hand, it is important to improve the routing performance by handling deadlocks if they occur. In this paper, a routing strategy for suspensive deadlock recovery called an escape-restoration routing is proposed and its performance is evaluated. In the principle of the proposed techniques, a small amount of exclusive buffer (escape-buffer) at each router is prepared for handling one of deadlocked packets. The transmission of the packet is suspended by temporarily escaping it to the escape-buffer. After the other deadlocked packets were sent, the suspended transmission resumes by restoring the escaped packet. Evaluation results show that the proposed techniques can improve the routing performance more than that of the previous recovery-based techniques in handling deadlocks.

This paper presents effective methods to calculate dual frame of the short-time Fourier expansion (STFE) in l2(Z). Based on a relationship between the prototype window used for generating a frame and the dual prototype window used for generating a dual frame in the STFE, two useful numerical methods with a finite frame operator are proposed to obtain finite support dual frames in time domain formulation. The methods can be used to construct the multiple STFE (MSTFE) suitable for a time-frequency analysis, synthesis and coding of discrete-time nonstationary signals. Numerical simulation results are given to verify the effectiveness of the calculation of dual frame.

A novel power spectral density accumulation (PSDA) method for estimating the bandwidth of the clutter spectra is proposed, based on a priori knowledge of the shape of the clutter spectra. The comparison of the complexity and the performance between the PSDA method and the general ones is presented. It is shown that the PSDA method is effective for the short-time clutter data in the practical application.

We report on the analysis and fabrication of vertical PtSi Schottky source/drain metal oxide semiconductor field effect transistors (MOSFETs), which are suitable for combination with quantum effect devices such as resonant tunneling diodes. Analysis was carried out by one-dimensional approximation of the device structure, WKB approximation of the tunneling probability in Schottky barrier tunneling and self-consistent calculation. Theoretical calculation showed good drivability (750 µA/µm) of this device with tOX = 1 nm and tSi = 5 nm. As a preliminary experiment, devices with a Si channel thickness of 8 nm, 20 nm or 30 nm and a vertical channel length of 55 nm were fabricated. Although the drain current at the "on" state was small due to the thick gate oxide of 8 nm, analysis and measurement showed reasonable agreement with respect to the drivability. Based on the results of theoretical analysis, the device drivability can be much improved by reducing the gate oxide thickness.

We consider the polymatroid packing and covering problems. The polynomial time algorithm with the best approximation bound known for either problem is the greedy algorithm, yielding guaranteed approximation factors of 1/k for polymatroid packing and H(k) for polymatroid covering, where k is the largest rank of an element in a polymatroid, and H(k)=Σi=1k 1/i is the kth Harmonic number. The main contribution of this note is to improve these bounds by slightly extending the greedy heuristics. Specifically, it will be shown how to obtain approximation factors of 2/(k+1) for packing and H(k)-1/6 for covering, generalizing some existing results on k-set packing, matroid matching, and k-set cover problems.