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[Keyword] SI(16314hit)

15361-15380hit(16314hit)

  • Document Image Segmentation and Layout Analysis

    Takashi SAITOH  Toshifumi YAMAAI  Michiyoshi TACHIKAWA  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    778-784

    A system for segmentation of document image and ordering text areas is described, and applied to complex printed page layouts of both Japanese and English. There is no need to make any assumptions about the shape of blocks, hence the segmentation technique can handle not only skewed images without skew-correction but also documents where columns are not rectangular. In this technique, based on the bottom-up strategy, the connected components are extracted from the reduced image, and classiferd according to their local information. The connected components calssified as characters are then merged into lines, and the lines are merged into areas. Extracted text areas are classified as body, caption, header or footer. A tree graph of the layout of the body texts is made, and the texts ordered by preorder traversal on the graph. We introduce the concept of an influence range of each node, a procedure for handling titles, thus obtaining good results on various documents. The total system is fast and compact.

  • A Fast Newton/LMS Algorithm

    Tae-Sung KIM  Seong-Dae KIM  

     
    PAPER-Adaptive Signal Processing

      Vol:
    E77-A No:7
      Page(s):
    1154-1156

    A fast Newton/LMS algorithm is proposed which uses an efficient inversion technique of input autocorrelation matrix when the periodic pseudo random sequence is used as the reference signal. The number of operations is greatly reduced and the computational results show fast convergence rate and low misadjustment error. And the application of the algorithm to the case of nonperiodic reference signal is described.

  • A Discrete Fourier Analyzer Based on Analog VLSI Technology

    Shoji KAWAHITO  Kazuyuki TAKEDA  Takanori NISHIMURA  Yoshiaki TADOKORO  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1049-1056

    This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

  • A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition

    Yoshifumi SASAKI  Michitaka KAMEYAMA  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1116-1122

    In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.

  • A Lexicon Directed Algorithm for Recognition of Unconstrained Handwritten Words

    Fumitaka KIMURA  Shinji TSURUOKA  Yasuji MIYAKE  Malayappan SHRIDHAR  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    785-793

    In this paper, authors discuss on a lexicon directed algorithm for recognition of unconstrained handwritten words (cursive, discrete, or mixed) such as those encountered in mail pieces. The procedure consists of binarization, presegmentation, intermediate feature extraction, segmentation recognition, and post-processing. The segmentation recognition and the post-processing are repeated for all lexicon words while the binarization to the intermediate feature extraction are applied once for an input word. This algorithm is essentially non hierarchical in character segmentation and recognition which are performed in a single segmentation recognition process. The result of performance evaluation using large handwritten address block database, and algorithm improvements are described and discussed to achieve higher recognition accuracy and speed. Experimental studies with about 3000 word images indicate that overall accuracy in the range of 91% to 98% depending on the size of the lexicon (assumed to contain correct word) are achievable with the processing speed of 20 to 30 word per minute on typical work station.

  • The Concept of Four-Terminal Devices and Its Significance in the Implementation of Intelligent Integrated Circuits

    Tadahiro OHMI  Tadashi SHIBATA  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1032-1041

    It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

  • Line Fitting Method for Line Drawings Based on Contours and Skeletons

    Osamu HORI  Satohide TANIGAWA  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    743-748

    This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

  • Development in Graph-and/or Network-Theoretic Research of Cellular Mobile Communication Channel Assignment Problems

    Masakazu SENGOKU  Hiroshi TAMURA  Shoji SHINODA  Takeo ABE  

     
    PAPER

      Vol:
    E77-A No:7
      Page(s):
    1117-1124

    The demand for mobile communication services is rapidly increasing, because the mobile communication service is synonymy of an ideal communication style realizing communication in anytime, anywhere and with anyone. The development of economic and social activities is a primary factor of the increasing demand for mobile communication services. The demand stimulates the development of technology in mobile communication including personal communication services. Thus mobile communication has been one of the most active research in communications in the last several years. There exist various problems to which graph & network theory is applicable in mobile communication services (for example, channel assignment algorithm in cellular system, protocol in modile communication networks and traffic control in mobile communication ). A model of a cellular system has been formulated using a graph and it is known that the channel assignment problem is equivalent to the coloring problem of graph theory. Recently, two types of coloring problems on graphs or networks related to the channel assignment problem were proposed. Mainly, we introduce these coloring problems and show some results on these problems in this paper.

  • A Signal Information Processing for the Stochastic Response Prediction of Double-Wall Type Sound

    Mitsuo OHTA  Shigeharu MIYATA  

     
    LETTER-Acoustics

      Vol:
    E77-A No:7
      Page(s):
    1194-1198

    In direct connection with the signal information processing, a practical method of identification and probabilistic prediction for sound insulation systems is theoretically proposed in the object-oriented expression forms by introducing a few functional system parameters. Concretely, a trial of identification of the above functional system parameters and the output probabilistic prediction for a panel thickness change of double-wall type sound insulation system, especially, under the existence of a strong background noise inside of the reception room, is newly proposed based on one of wide sense digital filters and SEA (Statistical Energy Analysis) method. Finally, by using the actual music sound of an arbitrary distribution type, the effectiveness of the proposad method is confirmed experimentally by applying it to some problems of predicting the cumulative probability distribution of the transmitted sound level fluctuation.

  • 200-kHz Wide-Band Underwater Ultrasonic Transducers for Color Video Picture Transmission

    Takeshi INOUE  Noriko WATARI  Akira KAMEYAMA  Michiya SUZUKI  Tetsuo MIYAMA  

     
    PAPER-Ultrasonics

      Vol:
    E77-A No:7
      Page(s):
    1185-1193

    Wide-band, low-ripple underwater transducers with high-power acoustic radiation capability have been designed on the basis of multiple-mode filter synthesis theory. They are composed of triple acoustic matching plates and double backing plates with optimized specific acoustic impedances,besides piezoelectric ceramic elements. One of the backing plates employs a Fe damping-alloy to suppress unwanted response peaks in the frequency range above the passband region. Two 33 array transducers were fabricated, each with a center frequency of 200 kHz, one as a transmitter and the other as a receiver. The two transducers show high-sensitivity, low-ripple and wide-band transmitting and receiving responses. Then, the transducers were applied in a color video picture digital transmission system.Clear color video pictures, composed of 256240 pixels, were successfully received within one second.

  • Graceful Degradation for Multiprocessor Realization of Maximally Flat FIR Digital Filters

    Saed SAMADI  Akinori NISHIHARA  Nobuo FUJII  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1083-1091

    In this paper we propose a method for increasing the reliability in multiprocessor realization of lowpass and highpass FIR digital filters possessing a maximally flat magnitude response. This method is based on the use of array realization of the filter which has been proposed earlier by the authors. It is shown that if a processing module of the array functions erroneously, it is possible to exclude the module and still obtain a lowpass FIR filter. However, as a price we should tolerate a slight degradation in the magnitude response of the filter that is equivalent to a wider transition band. We also analyze the behavior of the filter when our proposed schemes are implemented on more than one module. The justification of our approach is based on that a slight degradation of the spectral characteristics of a filter may be well tolerated in most filtering applications and thus a graceful degradation in the frequency domain can sufficiently reduce the vulnerability to errors.

  • 7.5 MFLIPS Fuzzy Microprocessor Using SIMD and Logic-in-Memory Structure

    Mamoru SASAKI  Fumio UENO  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1075-1082

    A fuzzy microprocessor is developed using 1.2 µm CMOS process. The inference scheme for the if-then fuzzy rules consists of three main steps i. e. if-part process, then-part process and defuzzification. In order to realize very high-speed inference and moderate programmability, we introduce three-type different structures i.e. SIMD, logic-in-memory and Wallace tree structures which are suitable for the three main steps. The inference speed including defuzzification is 7.5 MFLIPS which is 12.9 times higher than the previous VLSI implementation, and it can carry out many rules (960 rules) and many input and output variables (16 variables).

  • Voice Activity Detection and Transmission Error Control for Digital Cordless Telephone System

    Seishi SASAKI  Ichiro MATSUMOTO  Osamu WATANABE  Kenzo URABE  

     
    PAPER

      Vol:
    E77-B No:7
      Page(s):
    948-955

    Personal Handy Phone (PHP), the Japanese digital cordless telephone system is being developed. The 32kbits/s ADPCM (Adaptive Differential Pulse Code Modulation) codec has been standardized for PHP. This paper describes firstly, the advanced algorithms of a Voice Activity Detection (VAD) function that reduces power dissipation of a digital cordless telephone terminal, secondly, a comfort noise generator operates in conjunction with the VAD and finally, a transmission error control based on the use of the prediction coefficients generated in the ADPCM codec. These proposed algorithms function in the low signal-to-noise ratio (SNR) environment of personal radio communications. The quality of the reconstructed speech after the process is influenced by the VAD decision errors (false detection when no voice is present, or no detection when voice is present) , the similarity of the generated comfort noise to the actual background noise, and the transmission quality. The simulation results of the performance achieved by these algorithms are shown and required loading of the computation are also given.

  • A Memory-Based Recurrent Neural Architecture for Chip Emulating Cortical Visual Processing

    Luigi RAFFO  Silvio P. SABATINI  Giacomo INDIVERI  Giovanni NATERI  Giacomo M. BISIO  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1065-1074

    The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

  • A Study on the Performance Improvements of Error Control Schemes in Digital Cellular DS/CDMA Systems

    Ill-Woo LEE  Dong-Ho CHO  

     
    PAPER

      Vol:
    E77-B No:7
      Page(s):
    883-890

    In this paper, the average error-rate characteristics are investigated as the number of users increases in the digital cellular DS/CDMA (Direct Sequence/Code Division Multiple Access) systems. Then, the performances of the various error control schemes applied to the data service of digital cellular DS/CDMA systems are compared and analyzed. That is, the performances of the conventional error control schemes such as Go-back-N ARQ (Automatic Repeat Request) and Selective-Repeat ARQ are analyzed in the circumstance of digital cellular DS/CDMA system. Also, the improved error control schemes which utilize the variable window size and/or variable data packet size are proposed and evaluated in order to improve the performances of the conventional error control scheme such as Quick-Repeat ARQ and WORM ARQ schemes in the digital cellular DS/CDMA system environments. According to the simulation results, the performances of the improved scheme with variable window and variable frame size are superior to those of the conventional scheme in the view of throughput and delay characteristics due to the robustness to the fading channel impairments.

  • The Results of the First IPTP Character Recognition Competition and Studies on Multi-Expert Recognition for Handwritten Numerals

    Toshihiro MATSUI  Ikuo YAMASHITA  Toru WAKAHARA  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    801-809

    The Institute for Posts and Telecommunications Policy (IPTP) held its first character recognition competition in 1992 to ascertain the present status of ongoing research in character recognition and to find promising algorithms for handwritten numerals. In this paper, we report and analyze the results of this competition. In the competition, we adopted 3-digit handwritten postal code images gathered from live mail as recognition objects. Prior to the competition, 2,500 samples (7,500 characters) were distributed to the participants as traning data. By using about 10,000 different samples (29,883 characters), we tested 13 recognition programs submitted by five universities and eight manufacturing companies. According to the four kinds of evaluation criteria: recognition accuracy, recognition speed, robustness against degradation, and theroretical originality, we selected the best three recognition algorithms as the Prize of Highest Excellence. Interestingly enough, the best three recognition algorithms showed considerable diversity in their methodologies and had very few commonly substituted or rejected patterns. We analyzed the causes for these commonly substituted or rejected patterns and, moreover, examined the human ability to discriminate between these patterns. Next, by considering the complementary characteristics of each recognition algorithm, we studied a multi-expert recognition strategy using the best three recognition algorithms. Three kinds of combination rules: voting on the first candidate rule, minimal sum of candidate order rule, and minimal sum of dissimilarities rule were examined, and the latter two rules decreased the substitution rate to one third of that obtained by one-expert in the competition. Furthermore, we proposed a candidate appearance likelihood method which utilizes the conditional probability of each of ten digits given the candidate combination obtained by each algorithm. From the experiments, this method achieved surprisingly low values of both substitution and rejection rates. By taking account of its learning ability, the candidate appearance likelihood method is considered one of the most promising multi-expert systems.

  • Representing, Utilizing and Acquiring Knowledge for Document lmage Understanding

    Koichi KISE  Noboru BABAGUCHI  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    770-777

    This paper discusses the role of knowledge in document image understanding from the viewpoints of representation, utilization and acquisition. For the representation of knowledge, we propose two models, a layout model and a content model, which represent knowledge about the layout structure and content of a document, respectively. For the utilization of knowledge, we implement layout analysis and content analysis which utilize a layout model and a content model, respectively. The strategy of hypothesis generation and verification is introduced in order to integrate these two kinds of analysis. For the acquisition of knowledge, we propose a method of incremental acquisition of a layout model from a stream of example documents. From the experimental results of document image understanding and knowledge acquisition using 50 samples of visiting cards, we verified the effectiveness of the proposed method.

  • An Approach to Integrated Pen Interface for Japanese Text Entry

    Kazuharu TOYOKAWA  Kozo KITAMURA  Shin KATOH  Hiroshi KANEKO  Nobuyasu ITOH  Masayuki FUJITA  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    817-824

    An integrated pen interface system was developed to allow effective Japanese text entry. It consists of sub-systems for handwriting recognition, contextual post-processing, and enhanced Kana-to-Kanji conversion. The recognition sub-system uses a hybrid algorithm consisting of a pattern matcher and a neural network discriminator. Special care was taken to improve the recognition of non-Kanji and simple Kanji characters frequently used in fast data entry. The post-processor predicts consecutive characters on the basis of bigrams modified by the addition of parts of speech and substitution of macro characters for Kanji characters. A Kana-to Kanji conversion method designed for ease of use with a pen interface has also been integrated into the system. In an experiment in which 2,900 samples of Kanji and non-Kanji characters were obtained from 20 subjects, it was observed that the original recognition accuracy of 83.7% (the result obtained by using the pattern matching recognizer) was improved to 90.7% by adding the neural network discriminator, and that it was further improved to 94.4% by adding the post-processor. The improved recognition accuracy for non-Kanji characters was particularly marked.

  • Two Topics in Nonlinear System Analysis through Fixed Point Theorems

    Shin'ichi OISHI  

     
    PAPER

      Vol:
    E77-A No:7
      Page(s):
    1144-1153

    This paper reviews two topics of nonlinear system analysis done in Japan. The first half of this paper concerns with nonlinear system analysis through the nondeterministic operator theory. The nondeterministic operator is a set-valued or fuzzy set valued operator by K. Horiuchi. From 1975 Horiuchi has developed fixed point theorems for nondeterministic operators. Using such fixed point theorems, he developed a unique theory for nonlinear system analysis. Horiuchi's theory provides a fundamental view point for analysis of fluctuations in nonlinear systems. In this paper, it is pointed out that Horiuchi's theory can be viewed as an extension of the interval analysis. Next, Urabe's theory for nonlinear boundary value problems is discussed. From 1965 Urabe has developed a method of computer assisted existence proof for solutions of nonlinear boundary value problems. Urabe has presented a convergence theorem for a certain simplified Newton method. Urabe's theorem is essentially based on Banach's contraction mapping theorem. In this paper, reformulation of Urabe's theory using the interval analysis is presented. It is shown that sharp error estimation can be obtained by this reformulation. Both works discussed in this paper have been done independently with the interval analysis. This paper points out that they have deep relationship with the interval analysis. Moreover, it is also pointed out that these two works suggest future directions of the interval analysis.

  • Recognition of Elevation Symbols and Reconstruction of 3D Surface from Contours by Parallel Method

    Kazuhiko YAMAMOTO  Hiromitsu YAMADA  Sigeru MURAKI  

     
    PAPER

      Vol:
    E77-D No:7
      Page(s):
    749-753

    In this paper, symbols and numerals in topographic maps are recognized by the multi-angled parallelism (MAP) matching method, and small dots and lines are extracted by the MAP operation method. These results are then combined to determine the value, position, and attributes of elevation marks. Also, we reconstruct three dimensional surfaces described by contours, which is difficult even for humans since the elevation symbols are sparse. In reconstruction of the surface, we define an energy function that enfores three constraints: smoothness, fit, and contour. This energy function is minimized by solving a large linear system of simultaneous equations. We describe experiments on 25,000:1 scale topographic maps of the Tsukuba area.

15361-15380hit(16314hit)