This paper presents a verification and analysis tool set for embedded systems. Recently, the development scale of embedded systems has been increasing since they are used for mobile systems, automobile platforms, and various consumer systems with rich functionality. This has increased the amount of time and cost needed to develop them. Consequently, it is very important to develop tools to reduce development time and cost. This paper describes a tool set consisting of three tools to enhance the efficiency of embedded system design. The first tool is an integrated tool platform. The second is a remote debugging system. The third is a clock-accurate verification system based on a field-programmable gate array (FPGA) for custom embedded systems. This tool set promises to significantly reduce the time and cost needed to develop embedded systems.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

Iterative synthesis methods for making aware of wire congestion are proposed for a multi-context dynamically reconfigurable processor (DRP) with a large number of processing elements (PEs) and programmable-wire connections. Although complex data-paths can be synthesized using the programmable-wire, its delay is long especially when wire connections are congested. We propose two iterative synthesis techniques between a high-level synthesizer (HLS) and the place & route tool to shorten the prolonged wire delay. First, we feed back wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten by 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on the congestion. The synthesis time was shorten to 1/3 causing delay improvement rate degradation at two points on average.

This paper presents an interconnect resilient (IR) methodology with maximal interconnect fault tolerance, yield, and reliability for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this method can tolerate faulty connections by efficiently finding alternative paths. The proposed approach is compatible with previous interconnect detection and diagnosis methods under oscillation ring schemes, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple link faults in Network-on-Chips (NoCs). With such knowledge, designers can significantly improve interconnect reliability by augmenting vulnerable interconnect structures in NoCs. As a result, the experimental results show that alternative paths in NoCs can be found for almost all paths. Hence, the proposed method provides a good way to achieve fault tolerance and reliability/yield improvement.

This letter proposes a practical scheme that can estimate ADSL link rates. The proposed scheme allows us to estimate ADSL link rates from measurements made at the NOC using existing communications protocols and network node facilities; it imposes no heavy traffic overhead. The proposed scheme consists of two major steps. The first step is to collect measured data of round trip times (RTT) for both long and short packets to find their minimum values of RTTs by sending Internet Control Message Protocol (ICMP) echo request messages. The second step is to estimate the ADSL down- and up-link rates by using the difference in RTT between long and short packets and the experimentally-obtained correlated relationships between ADSL down- and up-link rates. RTTs are experimentally measured for an IP network, and it is shown that the down- and up-link rates can be obtained in a simple manner.

For the panoramic video streaming service, this letter proposes a visual perception-based view navigation trick mode (VP-VNTM) that reduces bandwidth requirements by adjusting the quality of transmitting views in accordance with the view navigation velocity without decreasing the user's visual sensitivity. Experiments show that the proposed VP-VNTM reduces bandwidth requirements by more than 44%.

A signal model and weighted-average based estimation techniques are proposed to estimate the angle-of-arrival (AOA) parameters of multiple clusters for a low data rate ultrawide band (LR-UWB) based wireless positioning system. The optimal AOA estimation techniques for the LR-UWB wireless positioning system according to the cluster condition are introduced and it is shown that the proposed techniques are superior to the conventional technique from the standpoint of performance.

In this paper, we propose a quantitative metric of measuring the degree of the visual fatigue in a stereoscopy. To the best of our knowledge, this is the first simplified relative quantitative approach describing visual fatigue value of a stereoscopy. Our experimental result shows that the correlation index of more than 98% is obtained between our Simplified Relative Visual Fatigue (SRVF) model and Mean Opinion Score (MOS).

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 4050%.

Traditional cellular networks suffer the so-called “cell-edge problem” in which the user throughput is deteriorated because of pathloss and inter-cell (co-channel) interference. Recently, Base Station Cooperation (BSC) was proposed as a solution to the cell-edge problem by alleviating the interference and improving diversity and multiplexing gains at the cell-edge. However, it has minimal impact on cell-inner users and increases the complexity of the network. Moreover, static clustering, which fixes the cooperating cells, suffers from inter-cluster interference at the cluster-edge. In this paper, dynamic fractional cooperation is proposed to realize dynamic clustering in a shared RRU network. In the proposed algorithm, base station cooperation is performed dynamically at cell edges for throughput improvement of users located in these areas. To realize such base station cooperation in large scale cellular networks, coordinated scheduling and distributed dynamic cooperation are introduced. The introduction of coordinated scheduling in BSC multi-user MIMO not only maximizes the performance of BSC for cell-edge users but also reduces computational complexity by performing simple single-cell MIMO for cell-inner users. Furthermore, the proposed dynamic clustering employing shared RRU network realizes efficient transmission at all cell edges by forming cooperative cells dynamically with minimal network complexity. Owing to the combinations of the proposed algorithms, dynamic fractional cooperation achieves high network performance at all areas in the cellular network. Simulation results show that the cell-average and the 5% cell-edge user throughput can be significantly increased in practical cellular network scenarios.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

A Wavelength division multiplexing passive optical network (WDM-PON) system that uses spectrum-sliced broadband incoherent light is attractive because it avoids the cost of operating/administering wavelengths in optical network units (ONU) at customer premises. However, it is difficult to enhance the spectrum efficiency to ensure a sufficient signal to noise ratio because it would demand broad channel width. To overcome this problem, we proposed a spectrum-interleaved duplex technique. It enables upstream and downstream communications to share one channel by using a cyclic filter. This sharing of one channel eliminates the need for a guard interval between signal lights duplexed in the channel. One residual issue regarding single band transmission is its robustness to reflection in the transmission medium. To increase the reflection robustness of the spectrum-interleaved duplex scheme, we propose a reflection remover based on an optical code division multiplexing technique. We also evaluate the extent to which capacity of the spectrum efficiency of the spectrum-interleaved duplex WDM-PON system that uses spectrum-sliced broadband incoherent light can be increased.

There are two major challenges in wide-band spectrum sensing in a heterogenous spectrum environment. One is the spectrum acquisition in the wide-band scenario due to limited sampling capability; the other is how to collaborate in a heterogenous spectrum environment. Compressed spectrum sensing is a promising technology for wide-band signal acquisition but it requires effective collaboration to combat noise. However, most collaboration methods assume that all the secondary users share the same occupancy of primary users, which is invalid in a heterogenous spectrum environment where secondary users at different locations may be affected by different primary users. In this paper, we propose an automatic clustering collaborative compressed spectrum sensing (ACCSS) algorithm. A hierarchy probabilistic model is proposed to represent the compressed reconstruction procedure, and Dirichlet process mixed model is introduced to cluster the compressed measurements. Cluster membership estimation and compressed spectrum reconstruction are jointly implemented in the fusion center. Based on the probabilistic model, the compressed measurements from the same cluster can be effectively fused and used to jointly reconstruct the corresponding primary user's spectrum signal. Consequently, the spectrum occupancy status of each primary user can be attained. Numerical simulation results demonstrate that the proposed ACCSS algorithm can effectively estimate the cluster membership of each secondary user and improve compressed spectrum sensing performance under low signal-to-noise ratio.

In the near future, interconnection networks of massively parallel computer systems will connect more than a hundred thousands of computing nodes. The performance evaluation of the interconnection networks can provide real insights to help the development of efficient communication library. Hence, to evaluate the performance of such interconnection networks, simulation tools capable of modeling the networks with sufficient details, supporting a user-friendly interface to describe communication patterns, providing the users with enough performance information, completing simulations within a reasonable time, are a real necessity. This paper introduces a novel interconnection network simulator NSIM, for the evaluation of the performance of extreme-scale interconnection networks. The simulator implements a simplified simulation model so as to run faster without any loss of accuracy. Unlike the existing simulators, NSIM is built on the execution-driven simulation approach. The simulator also provides a MPI-compatible programming interface. Thus, the simulator can emulate parallel program execution and correctly simulate point-to-point and collective communications that are dynamically changed by network congestion. The experimental results in this paper showed sufficient accuracy of this simulator by comparing the simulator and the real machine. We also confirmed that the simulator is capable of evaluating ultra large-scale interconnection networks, consumes smaller memory area, and runs faster than the existing simulator. This paper also introduces a simulation service built on a cloud environment. Without installing NSIM, users can simulate interconnection networks with various configurations by using a web browser.

Current density-voltage (J-V) and capacitance-voltage (C-V) characteristics of P3HT/n--silicon heterojunction diodes were investigated to clarify the carrier conduction mechanism at the organic/inorganic heterojunction. The J-V characteristics of the P3HT/n--Si junctions can be explained by a Schottky diode model with an interfacial layer. Diode parameters such as Schottky barrier height and ideality factor were estimated to be 0.78 eV and 3.2, respectively. The C-V analysis suggests that the depletion layer appears in the n--Si layer with a thickness of 1.2 µm from the junction with zero bias and the diffusion potential was estimated at 0.40 eV at the open-circuit condition. The present heterojunction allows a photovoltaic operation with power conversion efficiencies up to 0.38% with a simulated solar light exposure of 100 mW/cm2. The forward bias current was enhanced by coating the Si surface with a SiC layer, where the ideality factor was improved to be the level of 1.451.50.

We consider Downlink (DL) scheduling for a multi-user cooperative cellular system with fixed relays. The conventional scheduling trend is to avoid interference by allocating orthogonal radio resources to each user, although simultaneous allocation of users on the same resource has been proven to be superior in, e.g., the broadcast channel. Therefore, we design a scheduler where in each frame, two selected relayed users are supported simultaneously through the Superposition Coding (SC) based scheme proposed in this paper. In this scheme, the messages destined to the two users are superposed in the modulation domain into three SC layers, allowing them to benefit from their high quality relayed links, thereby increasing the sum-rate. We derive the optimal power allocation over these three layers that maximizes the sum-rate under an equal rates' constraint. By integrating this scheme into the proposed scheduler, the simulation results show that our proposed SC scheduler provides high throughput and rate outage probability performance, indicating a significant fairness improvement. This validates the approach of simultaneous allocation versus orthogonal allocation in the cooperative cellular system.

Inter-satellite link (ISL) is an important part of the next generation global navigation satellite system (GNSS). In this paper, key technologies of GNSS ISL ranging and time synchronization are researched. Considering that Ka frequency band is used for ISL, a fixed topology is designed and a new time division duplex (TDD) mode is proposed after analyzing the characteristics of GNSS constellations. A novel method called Non-coherent Dual One-way Measuring (NC-DOWM) is applied to this TDD mode. In addition, relevant mathematical formulas, error models and error compensation are discussed in detail. It is found that the proposed NC-DOWM method for GNSS ISL ranging and time synchronization outperforms the current method for GPS in terms of channel utilization efficiency and measuring precision. Furthermore, the presented method has excellent anti-interference capability and engineering feasibility, which can provide a strong technical support for the ISL of the next generation GNSS.

The interference rejection combining (IRC) receiver, which can suppress inter-cell interference, is effective in improving the cell-edge user throughput. The IRC receiver is typically based on the minimum mean square error (MMSE) criteria, which requires highly accurate channel estimation and covariance matrix estimation that includes the inter-cell interference. This paper investigates the gain from the IRC receiver in terms of the downlink user throughput performance in a multi-cell environment. In the evaluation, to assess the actual gain, the inter-cell interference signals including reference signals from the surrounding 56 cells are generated in the same way as the desired signals, and the channel propagation from all of the cells is explicitly taken into account considering pathloss, shadowing, and multipath fading. The results of simulations that assume the inter-site distance of 500 m, the spatial correlation at the transmitter and the receiver of 0.5, and the numbers of transmitter and receiver antennas of 2 and 2, respectively, show that the IRC receiver improves the cell-edge user throughput (defined as the 5% value in the cumulative distribution function) by approximately 15% compared to the simplified MMSE receiver that approximates the inter-cell interference as AWGN, at the cost of a drop in the average user throughput due to less accurate channel and covariance matrices. Furthermore, we consider dynamic switching between the IRC receiver and the simplified MMSE receiver according to the number of streams and modulation and coding scheme levels. The results show that with dynamic switching, both the cell-edge throughput and average user throughput are improved to the same level as that for the IRC receiver and the simplified MMSE receiver, respectively. Therefore, the best performance can be achieved by employing the dynamic switching in all throughput regions.

The message passing interface (MPI) broadcast communication commonly causes a severe performance bottleneck in multicore system that uses distributed memory. Thus, in this paper, we propose a novel algorithm and hardware structure for the MPI broadcast communication to reduce the bottleneck situation. The transmission order is set based on the state of each processing node that comprises the multicore system, so the novel algorithm minimizes the performance degradation caused by conflict. The proposed scoreboard MPI unit is evaluated by modeling it with SystemC and implemented using VerilogHDL. The size of the proposed scoreboard MPI unit occupies less than 1.03% of the whole chip, and it yields a highly improved performance up to 75.48% as its maximum with 16 processing nodes. Hence, with respect to low-cost design and scalability, this scoreboard MPI unit is particularly useful towards increasing overall performance of the embedded MPSoC.

Orthogonal frequency division multiple access (OFDMA) is adopted as a multiuser access scheme in recent cellular systems such as long term evolution (LTE) and WiMAX. In those systems, the performance improvement on cell-edge users is crucial to provide high-speed services. We propose a new resource allocation scheme based on multiple input multiple output – orthogonal frequency division multiple access – code division multiplexing (MIMO-OFDMA-CDM) to achieve performance improvements in terms of cell-edge user throughput, bit error rate, and fairness among users. The proposed scheme adopts code division multiplexing for MIMO-OFDMA and a modified proportional fairness algorithm for CDM, which enables the fairness among users and a higher throughput. The performance improvements are clarified by theoretical analysis and simulations.