Rapid developments in mobile technology have transformed mobile phones into mobile multimedia devices. Due to these advancements, user created mobile content is on the increase, both in terms of quality and quantity. To keep pace with such movements, the new networking technology named content centric networking (CCN), which is optimized for content sharing, has appeared. However, it virtually ignores mobile devices. So, this letter proposes a smooth mobile content migration scheme for CCN to provide lower communication overhead and shorter download time.

Due to an increase in multimedia content and the acceleration of digital convergence, demand for next-generation IPTV service is rapidly growing. IPTV service seamlessly provides both real-time broadcasting and content sharing services on diverse terminals through complex networks. In this paper, a secure and scalable content sharing framework is proposed for next-generation IPTV service. The proposed framework has an advantage over conventional content protection techniques in producing scalable content with transcodable, adjustable, and perceptual security features. Moreover, it ensures end-to-end security over the entire service range based on a single security mechanism. The suitability of the proposed approach is demonstrated experimentally using a practical service scenario with real-world environments. The experiments show that the proposed approach can provide several different levels of content security, from a perceptual level to an almost unintelligible level, while keeping the additional time overhead low. Consequently, it is expected that use of this security technology alone can have a practical contribution in creating new business opportunities for IPTV services.

We present an improvement to the existing steganography-based bandwidth extension scheme. Enhanced WB (wideband) speech quality is achieved by embedding multiple highband spectral gains into a G.711 bitstream. The number of spectral gains is selected by optimizing the quantity of the embedding data with respect to the quality of the extended WB speech. Compared to the existing method, the proposed scheme improves the WB PESQ (Perceptual Evaluation of Speech Quality) score by 0.334 with negligible degradation of the embedded narrowband speech.

We propose a flexible and scalable architecture for a network controller platform used for OpenFlow. The OpenFlow technology was proposed as a means for researchers, network service creators, and others to easily design, test, and virtually deploy their innovative ideas in a large network infrastructure, which will accelerate research activities on Future Internet architectures. The technology enables the independent evolution of the network control plane and the data plane. Rather than having programmability within each network node, the separated OpenFlow controller provides network control through pluggable software. Our proposed network controller architecture will enable researchers to use their own software to control their own virtual networks. Flexibility and scalability were achieved by designing the network controller as a modularized and distributed system on a cluster of servers. Testing showed that a group of servers can efficiently cooperate to serve as a scalable OpenFlow controller. Testing using the nationwide JGN2plus network demonstrated that high-definition video can be delivered through OpenFlow-based point-to-point and point-to-multipoint paths.

In algebraic attack on stream ciphers based on LFSRs, the secret key is found by solving an overdefined system of multivariate equations. There are many known algorithms from different point of view to solve the problem, such as linearization, relinearization, XL and Grobner Basis. The simplest method, linearization, treats each monomial of different degrees as a new variable, and consists of variables (the degree of the system of equations is denoted by d). Thus it needs at least equations, i.e. keystream bits to recover the secret key by Gaussian reduction or other. In this paper we firstly propose a concept, called equivalence of LFSRs. On the basis of it, we present a constructive method that can solve an overdefined system of multivariate equations with less keystream bits by extending the primitive polynomial.

In research community of content distribution, a new communication paradigm of rendezvous-based abstraction which easily enables location-free content-oriented services, attracts great attention. ID/Locator separation architecture is originally proposed for resolving increase of routing table size in the current Internet but it has possibility of supporting this abstraction because host ID is clearly separated from its location. This feature of ID/Locator separation means an end host can be identified by ID independent of its network layer protocol. So, ID/Locator separation architecture enables communication with end host(s) operating different network-layer protocol, which might increase candidate paths between host pairs and improve content distribution path. In this paper, we evaluate this improvement of shortest path brought by inter-layer 3 networking. In inter-layer 3 networking, a shared node connecting different network layer plane plays an important role. We evaluate shortest path improvement with various shared node locations and show that strategic assignment of shared nodes brings large improvement. When multiple layer 3 networks are available for users, shortest path might be improved even only with multi-homing (without inter-layer 3 networking). We also evaluate shortest path improvement brought by multi-homing and inter-layer 3 networking for incremental deployment scenario of multi-homing. Our simulation results show that inter-layer 3 networking brings great improvement even with small number of users deploying multi-homing while only multi-homing itself brings small improvement.

This paper proposes an adaptive sequential cooperative energy detection scheme for primary user detection in cognitive radio to minimize the detection time while guaranteeing the desired detection accuracy. Simulation results are provided to show the effectiveness of the proposed scheme.

Providing seamless QoS guarantees for multimedia services is one of the most critical requirements in the mobile Internet. However, the effects of host mobility make it difficult to provide such services. The next steps in signaling (NSIS) was proposed by the IETF as a new signaling protocol, but it fails to address some mobility issues. This paper proposes a new QoS NSIS signaling layer protocol (QoS NSLP) using a cross-layer design that supports mobility. Our approach is based on the advance discovery of a crossover node (CRN) located at the crossing point between a current and a new signaling path. The CRN then proactively reserves network resources along the new path that will be used after handoff. This proactive reservation significantly reduces the session reestablishment delay and resolves the related mobility issues in NSIS. Only a few amendments to the current NSIS protocol are needed to realize our approach. The experimental results and simulation study demonstrate that our approach considerably enhances the current NSIS in terms of QoS performance factors and network resource usage.

This paper proposes a novel waveguide intersection separating two H-plane waveguide systems from each other. If a four-port network in a four-fold rotational symmetry is completely matched, it has necessarily intersection properties. The proposed waveguide intersection consists of a square H-plane waveguide planar circuit connected four input/output waveguide ports in a four-fold rotational symmetry, and several metallic posts inserted at the junction without destroying the symmetry to realize a perfect matching. By optimizing the circuit parameters, high isolation properties are obtained in a relatively wide frequency band of about 8.6% for return loss and isolation better than 20 and 30 dB, respectively, for a circuit designed at 10 GHz. The proposed waveguide intersection can be analyzed by H-plane planar circuit approach, and possess advantages of compactness, simplicity, and high-power handling capability. Furthermore, an SIW intersection is designed by applying H-plane planar circuit approach to a waveguide circuit filled with dielectric material, and high isolation properties similar to H-plane waveguide intersection can be realized. The validity of these design concepts is confirmed by em-simulations and experiments.

This paper investigates characteristics of periodic structure of ferrite and dielectric slabs in cutoff waveguide which include left-handed operation. Transmission line model and finite element simulation are used to get dispersion characteristics and scattering parameters. Band pass response of left-handed ferrite mode at negative permeability region are discussed with backward wave phenomenon. Theoretical results show that by choosing appropriate ratio of (1) ferrite width and dielectric width, and (2) ferrite length and dielectric length, band pass response with steep edge characteristics can be obtained by the LH ferrite mode, which are confirmed with experiments using single crystal of yttrium iron garnet ferrite. Good band pass and phase shift responses are observed in S band.

An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

We present a simple constellation precoding technique for a coherent MIMO transmission scheme. Significant coding/diversity gains can be achieved with or without full channel state information. It is shown that the proposed scheme outperforms the conventional space-time block codes in the presence of continuous fading.

A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (Psat) under 1 V and 1.5 V supplies, respectively, and occupies a core chip area of 0.05 mm2. The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.

In this study, the design and fabrication of a 110–140-GHz varistor mode frequency tripler made with four Schottky diodes pair are presented. Nonlinear simulations were performed to calculate the optimum diode embedding impedance and the required input power. A compact microstrip resonant cell (CMRC) filter was introduced for the first time in submillimeter multiplier, instead of the traditional low-and-high impedance microstrip filter. The shorter size and the wider stop band of the CMRC filter improved the performance of the tripler. The tripler exhibited the best conversion efficiency of 5.2% at 129 GHz and peak output power of 5.3 mW at 125 GHz. Furthermore, within the output bandwidth from 110 to 140 GHz, the conversion efficiency was greater than 1.5%.

Kernel biased discriminant analysis (KBDA), as a subspace learning algorithm, has been an attractive approach for the relevance feedback in content-based image retrieval. Its performance, however, still suffers from the “small sample learning” problem and “kernel learning” problem. Aiming to solve these problems, in this paper, we present a new semi-supervised scheme of KBDA (S-KBDA), in which the projection learning and the “kernel learning” are interweaved into a constrained optimization framework. Specifically, S-KBDA learns a subspace that preserves both the biased discriminant structure among the labeled samples, and the geometric structure among all training samples. In kernel optimization, we directly optimize the kernel matrix, rather than a kernel function, which makes the kernel learning more flexible and appropriate for the retrieval task. To solve the constrained optimization problem, a fast algorithm based on gradient ascent is developed. The image retrieval experiments are given to show the effectiveness of the S-KBDA scheme in comparison with the original KBDA, and the other two state-of-the-art algorithms.

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.

In this paper, we propose a two dimensional (2D) non-separable adaptive directional lifting (ADL) structure for discrete wavelet transform (DWT) and its image coding application. Although a 2D non-separable lifting structure of 9/7 DWT has been proposed by interchanging some lifting, we generalize a polyphase representation of 2D non-separable lifting structure of DWT. Furthermore, by introducing the adaptive directional filteringingto the generalized structure, the 2D non-separable ADL structure is realized and applied into image coding. Our proposed method is simpler than the 1D ADL, and can select the different transforming direction with 1D ADL. Through the simulations, the proposed method is shown to be efficient for the lossy and lossless image coding performance.

Energy minimization has become one of the primary goals in the embedded real-time domains. Consequently, scratch-pad memory has been employed as partial or entire replacement for cache memory due to its better energy efficiency. However, most previous approaches were not applicable to a preemptive multi-task environment. We propose three methods of partitioning and allocation of scratch-pad memory for fixed-priority-based preemptive multi-task systems. The three methods, i.e., spatial, temporal, and hybrid methods, achieve energy reduction in the instruction memory subsystems. With the spatial method, each task occupies its exclusive space in scratch-pad memory. With the temporal method, the running task uses entire scratch-pad space. The content of scratch-pad memory is swapped out as a task executes or gets preempted. The hybrid method is based on the spatial one but a higher priority task can temporarily use the space of lower priority task. The amount of space is prioritized for higher priority tasks. We formulate each method as an integer programming problem that simultaneously determines (1) partitioning of scratch-pad memory space for the tasks, and (2) allocation of program code to scratch-pad memory space for each task. Our methods not only support the real-time task scheduling but also consider aggressively the periods and priorities of tasks for the energy minimization. Additionally, we implement an RTOS-hardware cooperative support mechanism for runtime code allocation to the scratch-pad memory space. We have made the experiments with the fully functional real-time operating system. The experimental results have demonstrated the effectiveness of our techniques. Up to 73% energy reduction compared to a conventional method was achieved.

We revisit the problem with generic object recognition from the point of view of human-computer interaction. While many existing algorithms for generic object recognition first try to detect target objects before features are extracted and classified in processing, our work is motivated by the belief that solving the task of detection by computer is not always necessary in many practical situations, such as those involving mobile recognition systems with touch displays and cameras. It is natural for these systems to ask users to input the segmentation data for targets through their touch displays. Speaking from the perspective of usability, such systems should involve rough segmentation to reduce the user workload. In this situation, different people would provide different segmentation data. Here, an interesting question arises – if multiple training samples are generated from a single image by using various segmentation data created by different people, what would happen to the accuracy of classification? We created “20 wild bird datasets” that had a large number of rough segmentation datasets made by 383 people in an attempt to answer this question. Our experiments revealed two interesting facts: (i) generating multiple training samples from a single image had positive effects on classification accuracies, especially when image features including spatial information were used and (ii) augmenting training samples with artificial segmentation data synthesized with a morphing technique also had slightly positive effects on classification accuracies.

This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.