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7381-7400hit(21534hit)

  • Statistical Analysis of Huge-Scale Periodic Array Antenna Including Randomly Distributed Faulty Elements

    Keisuke KONNO  Qiang CHEN  Kunio SAWAYA  Toshihiro SEZAI  

     
    PAPER-Microwave and Millimeter-Wave Antennas

      Vol:
    E94-C No:10
      Page(s):
    1611-1617

    On the huge-scale array antenna for SSPS (space solar power systems), the problem of faulty elements and effect of mutual coupling between array elements should be considered in practice. In this paper, the effect of faulty elements as well as mutual coupling on the performance of the huge-scale array antenna are analyzed by using the proposed IEM/LAC. The result shows that effect of faulty elements and mutual coupling on the actual gain of the huge-scale array antenna are significant.

  • HMM-Based Underwater Target Classification with Synthesized Active Sonar Signals

    Taehwan KIM  Keunsung BAE  

     
    LETTER-Digital Signal Processing

      Vol:
    E94-A No:10
      Page(s):
    2039-2042

    This paper deals with underwater target classification using synthesized active sonar signals. Firstly, we synthesized active sonar returns from a 3D highlight model of underwater targets using the ray tracing algorithm. Then, we applied a multiaspect target classification scheme based on a hidden Markov model to classify them. For feature extraction from the synthesized sonar signals, a matching pursuit algorithm was used. The experimental results depending on the number of observations and signal-to-noise ratios are presented with our discussions.

  • Iterative Determination of Phase Reference in IMD Measurement to Characterize Nonlinear Behavior, and to Derive Inverse, for Power Amplifier with Memory Effect

    Yasuyuki OISHI  Shigekazu KIMURA  Eisuke FUKUDA  Takeshi TAKANO  Yoshimasa DAIDO  Kiyomichi ARAKI  

     
    PAPER-Active Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1515-1523

    To reduce laborious tasks of the phase determination, our previous paper has proposed a method to derive phase reference for two-tone intermodulation distortion (IMD) measurement of a power amplifier (PA) by using small-signal S-parameters. Since the method is applicable to low output power level, this paper proposes an iterative process to extend the applicable power level up to 1-dB compression. The iterative process is based on extraction of linear response: the principle of the extraction is described theoretically by using an accurate model of the PA with memory effect. Measurement of two-tone IMD is made for a GaN FET PA. Validity of the iteration is confirmed as convergence of the extracted linear response to that given by the product of S21 and input signal. Measured results also show validity of the physical model of the memory effect provided by Vuolevi et al. because beat frequency dependences of IMD's are accurately fitted by bias impedances at even order harmonics of envelope frequency. The PA is characterized by using measured results and the third and fifth order inverses of the PA are designed. Improvement of IMD is theoretically confirmed by using the inverses as predistorters.

  • A 60 GHz High Gain Transformer-Coupled Differential Cascode Power Amplifier in 65 nm CMOS

    Jenny Yi-Chun LIU  Mau-Chung Frank CHANG  

     
    PAPER-Active Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1508-1514

    A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (Psat) under 1 V and 1.5 V supplies, respectively, and occupies a core chip area of 0.05 mm2. The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.

  • Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding

    Jia SU  Yiqing HUANG  Lei SUN  Shinichi SAKAIDA  Takeshi IKENAGA  

     
    PAPER-Image

      Vol:
    E94-A No:10
      Page(s):
    2013-2021

    With the increasing demand of high video quality and large image size, adaptive interpolation filter (AIF) addresses these issues and conquers the time varying effects resulting in increased coding efficiency, comparing with recent H.264 standard. However, currently most AIF algorithms are based on either frame level or macroblock (MB) level, which are not flexible enough for different video contents in a real codec system, and most of them are facing a severe time consuming problem. This paper proposes a content based coarse to fine AIF algorithm, which can adapt to video contents by adding different filters and conditions from coarse to fine. The overall algorithm has been mainly made up by 3 schemes: frequency analysis based frame level skip interpolation, motion vector modeling based region level interpolation, and edge detection based macroblock level interpolation. According to the experiments, AIF are discovered to be more effective in the high frequency frames, therefore, the condition to skip low frequency frames for generating AIF coefficients has been set. Moreover, by utilizing the motion vector information of previous frames the region level based interpolation has been designed, and Laplacian of Gaussian based macroblock level interpolation has been proposed to drive the interpolation process from coarse to fine. Six 720p and six 1080p video sequences which cover most typical video types have been tested for evaluating the proposed algorithm. The experimental results show that the proposed algorithm reduce total encoding time about 41% for 720p and 25% for 1080p sequences averagely, comparing with Key Technology Areas (KTA) Enhanced AIF algorithm, while obtains a BDPSNR gain up to 0.004 and 3.122 BDBR reduction.

  • A Novel Constellation Precoding Technique in MIMO Continuous Rayleigh Fading Channels

    Fuh-Hsin HWANG  Tsui-Tsai LIN  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E94-B No:10
      Page(s):
    2920-2924

    We present a simple constellation precoding technique for a coherent MIMO transmission scheme. Significant coding/diversity gains can be achieved with or without full channel state information. It is shown that the proposed scheme outperforms the conventional space-time block codes in the presence of continuous fading.

  • Design of an H-Plane Waveguide Intersection with High Isolation

    Hiroaki IKEUCHI  Tadashi KAWAI  Mitsuyoshi KISHIHARA  Isao OHTA  

     
    PAPER-Passive Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1572-1578

    This paper proposes a novel waveguide intersection separating two H-plane waveguide systems from each other. If a four-port network in a four-fold rotational symmetry is completely matched, it has necessarily intersection properties. The proposed waveguide intersection consists of a square H-plane waveguide planar circuit connected four input/output waveguide ports in a four-fold rotational symmetry, and several metallic posts inserted at the junction without destroying the symmetry to realize a perfect matching. By optimizing the circuit parameters, high isolation properties are obtained in a relatively wide frequency band of about 8.6% for return loss and isolation better than 20 and 30 dB, respectively, for a circuit designed at 10 GHz. The proposed waveguide intersection can be analyzed by H-plane planar circuit approach, and possess advantages of compactness, simplicity, and high-power handling capability. Furthermore, an SIW intersection is designed by applying H-plane planar circuit approach to a waveguide circuit filled with dielectric material, and high isolation properties similar to H-plane waveguide intersection can be realized. The validity of these design concepts is confirmed by em-simulations and experiments.

  • A Bayesian Model of Transliteration and Its Human Evaluation When Integrated into a Machine Translation System

    Andrew FINCH  Keiji YASUDA  Hideo OKUMA  Eiichiro SUMITA  Satoshi NAKAMURA  

     
    PAPER

      Vol:
    E94-D No:10
      Page(s):
    1889-1900

    The contribution of this paper is two-fold. Firstly, we conduct a large-scale real-world evaluation of the effectiveness of integrating an automatic transliteration system with a machine translation system. A human evaluation is usually preferable to an automatic evaluation, and in the case of this evaluation especially so, since the common machine translation evaluation methods are affected by the length of the translations they are evaluating, often being biassed towards translations in terms of their length rather than the information they convey. We evaluate our transliteration system on data collected in field experiments conducted all over Japan. Our results conclusively show that using a transliteration system can improve machine translation quality when translating unknown words. Our second contribution is to propose a novel Bayesian model for unsupervised bilingual character sequence segmentation of corpora for transliteration. The system is based on a Dirichlet process model trained using Bayesian inference through blocked Gibbs sampling implemented using an efficient forward filtering/backward sampling dynamic programming algorithm. The Bayesian approach is able to overcome the overfitting problem inherent in maximum likelihood training. We demonstrate the effectiveness of our Bayesian segmentation by using it to build a translation model for a phrase-based statistical machine translation (SMT) system trained to perform transliteration by monotonic transduction from character sequence to character sequence. The Bayesian segmentation was used to construct a phrase-table and we compared the quality of this phrase-table to one generated in the usual manner by the state-of-the-art GIZA++ word alignment process used in combination with phrase extraction heuristics from the MOSES statistical machine translation system, by using both to perform transliteration generation within an identical framework. In our experiments on English-Japanese data from the NEWS2010 transliteration generation shared task, we used our technique to bilingually co-segment the training corpus. We then derived a phrase-table from the segmentation from the sample at the final iteration of the training procedure, and the resulting phrase-table was used to directly substitute for the phrase-table extracted by using GIZA++/MOSES. The phrase-table resulting from our Bayesian segmentation model was approximately 30% smaller than that produced by the SMT system's training procedure, and gave an increase in transliteration quality measured in terms of both word accuracy and F-score.

  • Automatic Scale Detection for Contour Fragment Based on Difference of Curvature

    Kei KAWAMURA  Daisuke ISHII  Hiroshi WATANABE  

     
    PAPER-Pattern Recognition

      Vol:
    E94-D No:10
      Page(s):
    1998-2005

    Scale-invariant features are widely used for image retrieval and shape classification. The curvature of a planar curve is a fundamental feature and it is geometrically invariant with respect it the coordinate system. The curvature-based feature varies in position when multi-scale analysis is performed. Therefore, it is important to recognize the scale in order to detect the feature point. Numerous shape descriptors based on contour shapes have been developed in the field of pattern recognition and computer vision. A curvature scale-space (CSS) representation cannot be applied to a contour fragment and requires the tracking of feature points. In a gradient-based curvature computation, although the gradient computation considers the scale, the curvature is normalized with respect to not the scale but the contour length. The scale-invariant feature transform algorithm that detects feature points from an image solves similar problems by using the difference of Gaussian (DoG). It is difficult to apply the SIFT algorithm to a planar curve for feature extraction. In this paper, an automatic scale detection method for a contour fragment is proposed. The proposed method detects the appropriate scales and their positions on the basis of the difference of curvature (DoC) without the tracking of feature points. To calculate the differences, scale-normalized curvature is introduced. An advantage of the DoC algorithm is that the appropriate scale can be obtained from a contour fragment as a local feature. It then extends the application area. The validity of the proposed method is confirmed by experiments. The proposed method provides the most stable and robust scales of feature points among conventional methods such as curvature scale-space and gradient-based curvature.

  • Fast Shape Matching Using Statistical Features of Shape Contexts

    Moon-Jai LIM  Chan-Hee HAN  Si-Woong LEE  Yun-Ho KO  

     
    LETTER-Image Recognition, Computer Vision

      Vol:
    E94-D No:10
      Page(s):
    2056-2058

    A novel fast algorithm for shape matching using statistical features of shape contexts is presented. By pruning the candidate shapes using the moment-based statistical features of shape contexts, the required number of matching processes is dramatically reduced with negligible performance degradation. Experimental results demonstrate that the proposed algorithm reduces the pruning time up to 1/(r·n) compared with the conventional RSC algorithm while maintaining a similar or better performance, where n is the number of sampled points of a shape and r is the number of randomly selected representative shape contexts for the query shape.

  • Efficient and Secure Aggregation of Sensor Data against Multiple Corrupted Nodes

    Atsuko MIYAJI  Kazumasa OMOTE  

     
    PAPER-Information Network

      Vol:
    E94-D No:10
      Page(s):
    1955-1965

    Wireless Sensor Networks (WSNs) rely on in-network aggregation for efficiency, that is, readings from sensor nodes are aggregated at intermediate nodes to reduce the communication cost. However, the previous optimally secure in-network aggregation protocols against multiple corrupted nodes require two round-trip communications between each node and the base station, including the result-checking phase whose congestion is O(log n) where n is the total number of sensor nodes. In this paper, we propose an efficient and optimally secure sensor network aggregation protocol against multiple corrupted nodes by a random-walk adversary. Our protocol achieves one round-trip communication to satisfy optimal security without the result-checking phase, by conducting aggregation along with the verification, based on the idea of TESLA technique. Furthermore, we show that the congestion complexity, communication complexity and computational cost in our protocol are constant, i.e., O(1).

  • Robust Physical Layer Signaling Transmission over OFDM Systems

    Lifeng HE  Fang YANG  Zhaocheng WANG  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E94-B No:10
      Page(s):
    2900-2902

    In this letter, a novel physical layer signaling transmission scheme is proposed, where the signaling information is conveyed by a pair of training sequences located in the odd and even subcarriers of an orthogonal frequency division multiplexing (OFDM) training symbol. At the receiver side, only a single correlator is required to detect the signaling information. Computer simulations verify the proposed signaling could outperform the S1 signaling and achieve similar robustness as the S2 signaling of the DVB-T2 standard.

  • A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging

    Nguyen Ngoc MAI KHANH  Masahiro SASAKI  Kunihiro ASADA  

     
    PAPER-Microwave and Millimeter-Wave Antennas

      Vol:
    E94-C No:10
      Page(s):
    1626-1633

    This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.

  • A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

    Yang SUN  Chang-Jin JEONG  In-Young LEE  Sang-Gug LEE  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E94-C No:10
      Page(s):
    1698-1701

    In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.

  • A Wide Tuning Range CMOS Quadrature Ring Oscillator with Improved FoM for Inductorless Reconfigurable PLL

    Ramesh K. POKHAREL  Shashank LINGALA  Awinash ANAND  Prapto NUGROHO  Abhishek TOMAR  Haruichi KANAYA  Keiji YOSHIDA  

     
    PAPER-Active Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1524-1532

    This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

  • Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems

    Hideki TAKASE  Hiroyuki TOMIYAMA  Hiroaki TAKADA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E94-A No:10
      Page(s):
    1954-1964

    Energy minimization has become one of the primary goals in the embedded real-time domains. Consequently, scratch-pad memory has been employed as partial or entire replacement for cache memory due to its better energy efficiency. However, most previous approaches were not applicable to a preemptive multi-task environment. We propose three methods of partitioning and allocation of scratch-pad memory for fixed-priority-based preemptive multi-task systems. The three methods, i.e., spatial, temporal, and hybrid methods, achieve energy reduction in the instruction memory subsystems. With the spatial method, each task occupies its exclusive space in scratch-pad memory. With the temporal method, the running task uses entire scratch-pad space. The content of scratch-pad memory is swapped out as a task executes or gets preempted. The hybrid method is based on the spatial one but a higher priority task can temporarily use the space of lower priority task. The amount of space is prioritized for higher priority tasks. We formulate each method as an integer programming problem that simultaneously determines (1) partitioning of scratch-pad memory space for the tasks, and (2) allocation of program code to scratch-pad memory space for each task. Our methods not only support the real-time task scheduling but also consider aggressively the periods and priorities of tasks for the energy minimization. Additionally, we implement an RTOS-hardware cooperative support mechanism for runtime code allocation to the scratch-pad memory space. We have made the experiments with the fully functional real-time operating system. The experimental results have demonstrated the effectiveness of our techniques. Up to 73% energy reduction compared to a conventional method was achieved.

  • Modified Doubling Attack by Exploiting Chosen Ciphertext of Small Order

    Sung-Ming YEN  Wei-Chih LIEN  Chien-Ning CHEN  

     
    PAPER-Cryptography and Information Security

      Vol:
    E94-A No:10
      Page(s):
    1981-1990

    Power analysis can be used to attack many implementations of cryptosystems, e.g., RSA and ECC, and the doubling attack is a collision based power analysis performed on two chosen ciphertexts. In this paper, we introduced a modified doubling attack to threaten RSA and ECC implementations by exploiting only one chosen ciphertext of small order. To attack the RSA implementations we selected an input of order two while to attack the ECC implementations we exploited one chosen invalid point of small order on a cryptographically weak curve rather than on the original curve. We showed that several existing power analysis countermeasures for RSA and ECC implementations are still vulnerable to the proposed attack. To prevent the proposed attack, we suggested countermeasures for RSA as well as for ECC.

  • Augmenting Training Samples with a Large Number of Rough Segmentation Datasets

    Mitsuru AMBAI  Yuichi YOSHIDA  

     
    PAPER

      Vol:
    E94-D No:10
      Page(s):
    1880-1888

    We revisit the problem with generic object recognition from the point of view of human-computer interaction. While many existing algorithms for generic object recognition first try to detect target objects before features are extracted and classified in processing, our work is motivated by the belief that solving the task of detection by computer is not always necessary in many practical situations, such as those involving mobile recognition systems with touch displays and cameras. It is natural for these systems to ask users to input the segmentation data for targets through their touch displays. Speaking from the perspective of usability, such systems should involve rough segmentation to reduce the user workload. In this situation, different people would provide different segmentation data. Here, an interesting question arises – if multiple training samples are generated from a single image by using various segmentation data created by different people, what would happen to the accuracy of classification? We created “20 wild bird datasets” that had a large number of rough segmentation datasets made by 383 people in an attempt to answer this question. Our experiments revealed two interesting facts: (i) generating multiple training samples from a single image had positive effects on classification accuracies, especially when image features including spatial information were used and (ii) augmenting training samples with artificial segmentation data synthesized with a morphing technique also had slightly positive effects on classification accuracies.

  • Two Dimensional Non-separable Adaptive Directional Lifting Structure of Discrete Wavelet Transform

    Taichi YOSHIDA  Taizo SUZUKI  Seisuke KYOCHI  Masaaki IKEHARA  

     
    PAPER-Digital Signal Processing

      Vol:
    E94-A No:10
      Page(s):
    1920-1927

    In this paper, we propose a two dimensional (2D) non-separable adaptive directional lifting (ADL) structure for discrete wavelet transform (DWT) and its image coding application. Although a 2D non-separable lifting structure of 9/7 DWT has been proposed by interchanging some lifting, we generalize a polyphase representation of 2D non-separable lifting structure of DWT. Furthermore, by introducing the adaptive directional filteringingto the generalized structure, the 2D non-separable ADL structure is realized and applied into image coding. Our proposed method is simpler than the 1D ADL, and can select the different transforming direction with 1D ADL. Through the simulations, the proposed method is shown to be efficient for the lossy and lossless image coding performance.

  • A Low-Noise, High-Gain Quasi-Millimeter-Wave Receiver MMIC with a Very High Degree of Integration Using 3D-MMIC Technology

    Takana KAHO  Yo YAMAGUCHI  Kazuhiro UEHARA  Kiyomichi ARAKI  

     
    PAPER-Active Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1548-1556

    We present a highly integrated quasi-millimeter-wave receiver MMIC that integrates 22 circuits in a 3 2.3 mm area using three-dimensional MMIC (3D-MMIC) technology. The MMIC achieves low noise (3 dB) and high gain (41 dB) at 26 GHz by using an on-chip image reject filter. It integrates a multiply-by-eight (X8) local oscillator (LO) chain with the IF frequency of the 2.4 GHz band and can use low-cost voltage-controlled oscillators (VCOs) and demodulators in a 2–3 GHz frequency band. Multilayer inductors contribute to the miniaturization especially in a 2–12 GHz frequency band. Furthermore, it achieves a high dynamic range by using two step attenuators with a new built-in inverter using an N-channel depression field-effect transistor (FET). The power consumption of the MMIC is only 450 mW.

7381-7400hit(21534hit)