High power consumption is a constraining factor for the growth of programmable logic devices. We propose two techniques in order to reduce power consumption. The first is a technique for creating contexts. This technique uses data-dependent circuits and wire sharing between contexts. The second is a technique for switching the contexts. In this paper, we evaluate the capability of the two techniques to reduce power consumption using a multi-context logic device. As a result, as compared with the original circuit, our multi-context circuits reduced the power consumption by 9.1% on an average and by a maximum of 19.0%. Furthermore, applying our resource sharing technique to these circuits, we achieved a reduction of 10.6% on an average and a maximum reduction of 18.8%.

Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.

The present paper describes an implementation of an intrusion detection system (IDS) on an FPGA for 10 Gigabit Ethernet. The system includes an exact string matching circuit for 1,225 Snort rules on a single device. A number of studies have examined string matching circuits for IDS. However, implementing a circuit that processes a large rule set at high throughput is difficult. In a previous study, we proposed a method for generating an NFA-based string matching circuit that has expandability of processing data width and drastically reduced resource requirements. In the present paper, we implement an IDS circuit that processes 1,225 Snort rules at 10 Gbps with a single Xilinx Virtex-II Pro xc2vp-100 using the NFA-based method. The proposed circuit also provides packet filtering for an intrusion protection system (IPS). In addition, we developed a tool for automatically generating the Verilog HDL source code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit generator, the proposed system is able to update the matching rules corresponding to new intrusions and attacks. We implemented the IDS circuit on an FPGA board and evaluated its accuracy and throughput. As a result, we confirmed in a test that the circuit detects attacks perfectly at the wire speed of 10 Gigabit Ethernet.

Ubiquitous computing and the upcoming broadcast-and-communication convergence require networks that provide very complex services. In particular, networks are needed that can service several users or terminals at various times or places with various application-layer functions that can be changed at a high response speed by adding high-speed processing at the network edge. I present a query-transaction acceleration appliance that uses a dynamic reconfigurable processor (DRP) and enables high-speed stateful packet-by-packet self-reconfiguration to achieve that requirement. This appliance processes at high speeds, has flexible application layer functions that are changeable with a high-speed response, and uses direct packet I/O bypassing memory, hierarchical interconnection of processors, and stateful packet-by-packet self-reconfiguration. In addition, the DRP enables the fabrication of a compact and electric-power-saving appliance. I made a prototype and implemented several transport/application layer functions, such as TCP connection control, auto-caching of server files, uploading cache data for server, and selection/insertion/deletion/update of data for a database. In an experimental evaluation in which four kinds of query-transactions were continually executed in order, I found that the appliance achieved four functions changeable at a high response speed (within 1 ms), and a processing speed (2,273 transactions/sec.) 18 times faster than a PC with a 2-GHz processor.

A new unified method is proposed to calculate the basic resonator parameters, i.e., the resonant frequency, external Q, unloaded Q and coupling coefficient in the time domain. By exciting the resonator from a weakly coupled external circuit, one can inject only a narrow resonant spectrum from the broad spectrum of the excitation pulse. The resonant frequency is easily counted by the number of zero crossings of the internal field intensity, whereas the Q's are calculated by the decay rate of the field amplitude. The coupling coefficient computed by the energy exchange rate between two resonators completes the new time domain algorithm.

A periodically loaded ultra wideband (UWB) bandpass filter based on the electromagnetic band-gap (EBG) concept is presented. Compact wideband filters with steep transition bands can be designed easily using this novel methodology. Unit cells in the EBG circuit model are realized by capacitive and inductive parallel loading of a transmission line. These unit cells are cascaded to realize bandpass filters whose bandwidth depends on the reactive loading of unit cells. The number of unit cells determines the steepness of the band edges of the filter. The main advantage lies in the fact that the size of unit cells can be small because electrical length of transmission line segments in unit cells can be chosen arbitrarily, hence the final filter structure becomes small in size. A microstrip filter with 60% bandwidth is designed and the physical size is compared with a conventional wideband bandpass filter designed with quarter wavelength admittance inverters.

This paper presents the ultrawideband filters for UWB fullband (range of 3.1-10.6 GHz) applications. This filter consists of ring filter for wide-bandwidth and coupled line structure for suppressing unwanted passband in upper and lower stopbands. Especially, the filter structure was realized on silicon substrate using thin film technology, adequate for wafer level packaging, which can be integrated with CMOS UWB chipset that is currently on development. To minimize the dimension of the filter, the Hilbert structure was applied in ring filter and the meander shaped broadside coupled structure was also adopted in the coupled line structure. The size of the fully realized filter structure is 4.43.6 mm2. The insertion loss in passband is 1.5 dB and the return loss is larger than 15 dB, respectively. The group delay in center frequency is 0.2 ns and the group delay variation is less than 0.15 ns.

A wideband NRD guide and rectangular waveguide H-plane transition is proposed to transfer millimeter waves from a dielectric strip to the outer conductor surface of NRD guide through a short length of waveguide made through the conductor plate. As a result, it has a bandwidth about 6.7 GHz of |S11| -15 dB and a low transition loss about 0.35 dB at 60 GHz band.

This study presents a class of miniature parallel-coupled bandpass filters with good selectivity and stopband rejection. Capacitive terminations are introduced to the conventional anti-parallel coupled-lines, and lumped-element K-inverters are employed, to achieve both size reduction and spurious suppression. Additionally, the capacitive cross-coupling effect can be introduced to obtain three transmission zeros to enhance the selectivity. Suitable equivalent-circuit models, along with design formulae, are also established. Specifically, via design examples, this work demonstrates the feasibility of proposed filter structures in microstrip configuration. Compared to the conventional parallel-coupled filters, the proposed filters exhibit over 60% size reduction, improved selectivity, and wider stopbands up to four times the center frequency.

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.

Owing to simple structure, low cost and high performance, NRD-guide millimeter wave circuits have attracted much attention in recent years. In this paper, a variety of NRD-guide passive components are reviewed with emphasis on design techniques and performance estimation in the 60 GHz frequency band where the license-free advantage is available. The passive components to be discussed here include compact bends, wideband hybrid couplers, practical three-port junctions, versatile E-plane filters, and effective feeding structures for lens antennas. Some of them are employed to construct millimeter wave transceivers. Eye patterns observed at 1.5 Gbps confirm the potential ability of the fabricated NRD-guide transceivers for high bit-rate, wireless applications.

Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied; a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%.

In this paper, an inverse S-shaped slotted ground structure (S-SGS) is proposed and analyzed. The S-SGS generates dual attenuation poles that can be easily controlled by its structure parameters. The equivalent circuit of the S-SGS consists of lumped elements that can be extracted from the measured S parameters. Moreover, several S-SGS cells are applied to form a miniaturized lowpass filter (LPF), which has a smaller area and a wider stopband in comparison to previous works.

In this paper, we consider consecutive burst transmission with burst loss recovery based on Forward Error Correction (FEC) in which redundant data is transmitted with multiple bursts. We propose two burst generation methods: Out-of Burst Generation (OBG) and In-Burst Generation (IBG). The OBG generates a redundant burst from redundant data, while the IBG reconstructs a burst from an original data block and a part of the redundant data. For both methods, the resulting bursts are transmitted consecutively. If some bursts among the bursts are lost at an intermediate node, the lost bursts can be recovered with the redundant data using FEC processing at the destination node. We evaluate by simulation the proposed methods in a uni-directional ring network and NSFNET, and compare the performances of the proposed methods with the extra-offset time method. Numerical examples show that the proposed methods can provide a more reliable transmission than the extra-offset time method for the OBS network where the maximum number of hops is large. Moreover, it is shown that the end-to-end transmission delay for our proposed methods can be decreased by enhancing the FEC processor or by increasing the number of FEC processors.

In ubiquitous networks, Mobile Nodes (MNs) often suffer from performance degradation due to the following two reasons: (1) reduction of signal strength by the movement of an MN and intervening objects, and (2) radio interference with other WLANs. Therefore, handover initiation based on quick and reliable detection of the deterioration in a wireless link condition arising from the above two reasons is essential for achieving seamless handover. In previous studies, we focused on a handover decision criterion and described the problems related to the two existing decision criteria. Furthermore, we showed the effectiveness of the number of frame retransmissions through simulation experiments. However, a comparison of the signal strength and the number of frame retransmissions could not be examined due to the unreliability of the signal strength in simulations. Therefore, in the present paper, by employing FTP and VoIP applications, we compare the signal strength and the number of frame retransmissions as a handover decision criterion with experiments in terms of (1) and (2) in a real environment. Finally, we clarify the problem of the signal strength in contrast to the effectiveness of the number of frame retransmissions as a handover decision criterion.

In this paper, we describe a single system image (SSI) architecture for distributed systems. The SSI architecture is constructed through three components: single process space (SPS), process migration, and dynamic load balancing. These components attempt to share all available resources in the cluster among all executing processes, so that the distributed system operates like a single node with much more computing power. To this end, we first resolve broken pipe problems and bind errors on server socket in process migration. Second, we realize SPS based on block process identifier (PID) allocation. Finally, we design and implement a dynamic load balancing scheme. The dynamic load balancing scheme exploits our novel metric, effective tasks, to effectively distribute jobs to a large distributed system. The experimental results show that these three components present scalability, new functionality, and performance improvement in distributed systems.

We propose a filtering method for optimal estimation of TFT-LCD's surface region except defect's region. To estimate the non-uniform intensity variation on TFT-LCD surface region, the 4-directional Gaussian filter based on image pyramid structure is proposed. The experimental result verified the proposed method's performance

A new BIST (Built-in Self-test) method for static ADC testing is proposed. The proposed method detects offset, gain, INL (Integral Non-linearity) and DNL (Differential Non-linearity) errors with a low hardware overhead. Moreover, it can solve a transient zone problem which is derived from the ADC noise in real test environments.

Due to the ultra low power spectral desity of the ultra-wide band (UWB), narrow band interference (NBI) with high-level emission power will degrade the accuracy of UWB ranging system. We propose a novel waveform to suppress the accuracy degradation by NBI with a given frequency. In addition, we compare the ranging error ratio (RER) of the proposed scheme with the traditional one with Gaussian monocycle in this letter.

This letter deals with adaptive array beamforming based on a minimum variance distortionless response (MVDR) technique with robust capabilities for code-division multiple access signals. It has been shown that the MVDR beamformer suffers from the drawback of being very sensitive to pointing error over the eigenspace-based beamformers. For the purpose of efficient estimation and calibration, a highly efficient approach has been proposed that is implemented on polynomial rooting rather than spectral searching. However, this rooting method is suboptimal in the presence of the noise and multiple access interference (MAI). In this letter, we propose an improved polynomial rooting calibration method that is robust in both of the low signal-to-noise ratio and large MAI scenarios. Several computer simulations are provided for illustrating the effectiveness of the proposed method.