This paper proposes a heuristic algorithm which, given a basis of a subspace of the space of cuspforms of weight 2 for 0(N) which is invariant for the action of the Hecke operators, tests whether the subspace corresponds to a quotient A of the jacobian of the modular curve X0(N) such that A is the jacobian of a curve C. Moreover, equations for such a curve C are computed which make the quotient suitable for applications in cryptography. One advantage of using such quotients of modular jacobians is that fast methods are known for finding their number of points over finite fields.

This paper presents a new framework for synthesizing look-up table (LUT) networks. Some of the existing LUT network synthesis methods are based on one or two functional (Boolean) decompositions. Our method also uses functional decompositions, but we try to use various decomposition methods, which include algebraic decompositions. Therefore, this method can be thought of as a general framework for synthesizing LUT networks by integrating various decomposition methods. We use a cost database file which is a unique characteristic in our method. We also present comparisons between our method and some well-known LUT network synthesis methods, and evaluate the final results after placement and routing. Although our method is rather heuristic in nature, the experimental results are encouraging.

Spatiotemporal chaos in a multidomain regime in a Gunn-effect device is numerically investigated as an example of collective domain oscillations under global constraints. The dynamics of carrier densities are computed using a set of model partial differential equations. Numerical results reveal some distinctive and chaotic clustering features caused by the global coupling and boundary effects. The chaotic regime is then characterized in terms of a Lyapunov spectrum and Lyapunov dimension, the latter increasing with the size of the system.

The legal firing sequence problem of Petri nets (LFS) is one of fundamental problems in the analysis of Petri nets, because it appears as a subproblem of various basic problems. Since LFS is shown to be NP-hard, various heuristics has been proposed to solve the problem of practical size in a reasonable time. In this paper, we propose a new algorithm for this problem. It is based on the partial order verification technique, and reduces redundant branches in the search tree. Moreover, the proposed algorithm can be combined with various types of heuristics.

Petri net is a mathematical model for concurrent systems. Liveness is one of important properties of Petri net. Liveness problem of general Petri net is of exponential space complexity and subclasses are suggested with less computational complexity. It is well known that liveness problem of bounded (extended) free choice net is solved in deterministic polynomial time. This paper treats liveness problem of AC/DC nets. AC/DC net is a subclass of Petri net that exhibits no confusion (mixture of concurrency and conflict). This class properly includes the class of free choice nets. It is shown that every minimal siphon of an AC/DC net is trap if and only if every strongly connected siphon is a trap. This result shows that monotone liveness of bounded AC/DC net is solved in deterministic polynomial time. It is shown that this result is true of bounded time AC/DC net with static fair condition.

Topological sorting is, given with a directed acyclic graph G=(V,E), to find a total ordering of the vertices such that if (u,v)E then u is ordered before v. Instead of topological sorting, we are interested in how many total orderings exist in a given directed acyclic graph. We call such a total ordering as legal sequence and the problem of finding total number of legal sequences as legal sequence number problem. In this paper, we firstly give necessary definitions and known results obtained in our previous research. Then we give a method how to obtain legal sequence number for a class of directed acyclic graphs, extended 2-b-SPGs. Finally we discuss the complexity of legal sequence number problem for extended 2-b-SPGs.

Agent technology is widely recognized as a new paradigm for the design of concurrent software and systems. The aim of this paper is to give a mathematical foundation for the design and the analysis of multi-agent systems by means of a Petri-net-based model. The proposed model, called PN2, is based on place/transition nets (P/T nets), which is one of the simplest classes of Petri nets. The main difference of PN2's from P/T nets is that each token, representing an agent, is also a P/T net. PN2's are sufficiently simple for the mathematical analysis, such as invariant analysis, but have enough modeling power.

This letter proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more types of functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which consider only one type of functional units for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.

Cyclic shifters are required in many central parts of microprocessors, floating-point units and DSPs. The main difficulty in conventional cyclic shifter designs are the long internal wire connections. For this reason we propose cyclic shifter layouts that improve the accumulated wire length on the critical path by rearranging the placement of the logical gates. We can show that in this way the wire length complexity on the critical path can be reduced from Ω(n log (n)) in conventional designs to O(n) in our optimized designs where n is the width of the shifted operand. For the practical case of n=64 we shorten the accumulated wire length on the critical path by a factor of 2.20. In the same design the maximal size of a net that has to be driven by a single gate is cut down by a factor of 1.86. This leads to faster cyclic shifter designs with lower power dissipation.

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.

This document analyzes the characteristics of Waiting Time Jitter (WTJ) generated in High-bit-rate Digital Subscriber Lines (HDSL) systems transmitting non-uniform frames. It also derives the Fourier transform of the above WTJ.

Due to the advancements in Information Technology, such as the Internet and the presence of fierce competition in the market, the business environment is changing rapidly. To cope with these dynamic changes, heterogeneous systems are now required to integrate in order to form alliances with different business units or within individual business units. Since business operations can not be stopped to carry out these changes in the existing systems, the systems are required to integrate flexibly, preserving each constituent's individual characteristics. By implementing Atomic Action through a gateway and across constituent systems in a Heterogeneous Autonomous Decentralized System (HADS), higher degrees of assurance can be achieved through cooperation. However, if all the transactions are passed through a gateway, the response time worsens and the result cannot be obtained within an appropriate timeframe. Hence, a new technique of suppressing the flow passing through the gateway, while achieving a maximum number of successful transaction within the appropriate timeframe, is required.

Power supply rejection ratio (PSRR) characteristics of a switched capacitor filter (SCF) is improved when using an equal level diagram design of a leapfrog type filter. By using this design method, it is shown that PSRR of a SCF measured is improved about 20 dB.

Using a point matching method, we have numerically analyzed resonance frequencies and unloaded Q factor of whispering gallery modes in a millimeter wave region that are well known as an intrinsic mode of a dielectric disk resonator. We express field distributions of the resonance modes by a summation of spherical waves. Tangential electromagnetic fields inside the disk are matched to those outside the disk at appropriate matching points on a boundary. As the result, a 4N 4N (N; number of matching points) determinant is derived as an eigenvalue equation of the disk resonator. Since elements of the determinant are complex numbers, a complex angular frequency is introduced to make a value of the determinant zero. For a location of the matching points, we also introduce a new technique which is derived from a field expression of the whispering gallery modes. Since an azimuthal angle dependence of the field distributions with a resonance mode number m is presented by the associated Legendre function Pnm(cos θ), we define abscissas θi of the matching points as solutions of Pm+2N-1m (cos θ) = 0. Considering the field symmetry, we also modify the eigenvalue equation to a new eigenvalue equation which is expressed (4N - 2) (4N - 2) determinant. From the results of our numerical analysis, we can find that the resonance frequencies and unloaded Q factor well converge for number of matching points N. A comparison of numerical results and experimental ones, in a millimeter wave band (50 - 100 GHz), shows a good agreement with each other. It is found that our analysis is effective for practical use in the same wave band.

Successful e-commerce presupposes techniques by which autonomous trading entities can interoperate. Although progress has been made on data exchange and payment protocols, interoperation in the face of autonomy is still inadequately understood. Current techniques, designed for closed environments, support only the simplest interactions. We develop a multiagent approach for interoperation of business process in e-commerce. This approach consists of (1) a behavioral model to specify autonomous, heterogeneous agents representing different trading entities (businesses, consumers, brokers), (2) a metamodel that provides a language (based on XML) for specifying a variety of service agreements and accommodating exceptions and revisions, and (3) an execution architecture that supports persistent and dynamic (re)execution.

A new architecture and methods for an enhanced autonomous decentralized production system (EADPS) are described. This EADPS was developed to ensure high flexibility of production systems consisting of intelligent devices based on the autonomous decentralized system model and to guarantee the time used for communication to simultaneously maintain high productivity. The system architecture of the EADPS guarantees the time by managing groups of nodes and the priorities in these groups. A bit-arbitration method is used to prevent collision of messages. The nodes autonomously check the waveforms in the network and terminate transmission when the nodes with a higher priority are transmitting. A parallel-filtering method is used to speed up message acceptance. The nodes check the identifiers of the messages using parallel-filtering circuits and each node determines autonomously where a message should be accepted or not. Implementing the system architecture and these methods as circuits and integrating the circuits into a chip using system LSI technologies resulted in low-cost implementation of the system. Experimental evaluation demonstrated the effectiveness of this system.

The boundary integral equation (BIE) on interior walls with surface impedance conditions is implemented to the iterative physical optics method and how to treat the singularities involved in the BIE of an impedance cavity is described. Singular integrals over a rectangular region can be represented by simple elementary functions.

We study the reliability functions or the minimum r-achievable rates of the lossless coding for the general sources in the sense of Han-Verdu, where r means the exponent of the error probability. Han has obtained formulas for the minimum r-achievable rates of the general sources. Our aim is to give alternative expressions for the minimum r-achievable rates. Our result seems to be a natural extension of the known results for the stationary memoryless sources and Markov sources.