Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.

A dual-offset microstrip-fed slot antenna having large bandwidth studied in this paper. The proposed antenna is analyzed by the Finite Difference Time Domain (FDTD) method. In this case, two offsets and other design parameters of the antenna lead to the good impedance matching over a wide frequency band. The experimental bandwidth is approximately 1.587 octave (-10 dB S11). And the experimented data for the impedance loci, the radiation patterns, and gain of the antenna are also described. The measured results are relatively in good agreement with the FDTD results.

Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.

We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.

A novel in vivo exposure setup has been developed for testing the possible promoting effects of 1.5 GHz digital cellular phones on mouse skin carcinogenesis. The exposure setup has two main features: one is the employment of an electrically short monopole antenna with capacitive-loading, which supplies the ability to realize a highly localized peak SAR above 2 W/kg without any thermal stress for a mouse; the other is the use of a transparent absorber to allow real-time observation of both the exposure process as well as mouse activities during the exposure. Dosimetric analyses for the exposure setup have been carried out both numerically and experimentally. Good agreement was confirmed between the numerical and experimental results, thereby demonstrating the validity of the novel exposure setup.

Due to a large capacitance and enormous access rate, caches dissipate about a third of the total energy consumed by today's processors. In this paper we present a new architectural technique to reduce energy consumption in caches. Unlike previous approaches, which have focused on lowering cache capacitance and the number of accesses, our method exploits a new freedom in cache design, namely the voltage per access. Since in modern block-buffered caches, the loading capacitance operated on block-hit is much less than the capacitance operated on miss, the given clock cycle time is inefficiently utilized during the hit. We propose to trade-off this unused time with the supply voltage, lowering the voltage level on the hit and increasing it on the miss. Experiments show that the approach can half the cache energy dissipation without large performance and area overhead.

Turbo coding is widely known as one of effective error control coding techniques in various digital communication systems since this coding method has proposed by C. Berrou, etc in 1993. In digital magnetic recording, it has been cleared that the error correcting capability of turbo coding is superior to most of conventional recording codes as a matter of course. But, the performance of a partial response maximum-likelihood (PRML) system combined with any recording code is degraded by many undesirable factors or effects. To improve the performance of the PRML system in high areal density recording, it is useful to adopt a higher order PRML system or high rate code in a general case. In this paper, the rate 32/34 turbo code combined with an enhanced extended class-4 partial response (E2PR4) is proposed. We call this trellis coded partial response (TCPR) system the rate 32/34 turbo-coded E2PR4 (32/34 TC-E2PR4). Our proposed TCPR system can be expected to get large coding gain and improve the performance of PRML system. As a result, the proposed coding system provides a good performance compared with the conventional systems. In especial, our system can achieve a BER of 10-5 with SNR of approximately 1.5 dB less than the conventional 8/9 maximum transition run (MTR) coded E2PR4ML system at a normalized linear density of 3.

In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.

Reversible variable length codes (RVLCs), which make instantaneous decoding possible in both forward and backward directions, are exploited to code data stream in noisy enviroments. Because there is no redundancy in code words of RVLCs, RVLCs are suitable for very low bit-rate video coding. Golomb-Rice code, one of variable length code for infinite number of symbols, is widely used to encode exponentially distributed non-negative integers. We propose a reversible variable length code by modifying Golomb-Rice code, which is called parity check reversible Golomb-Rice code and abbreviated to P-RGR code. P-RGR code has the same code length distribution as GR code but can detect one-bit error in any arbitrary position of the code stream. The sets of P-RGR code words in both directions are identical so that they can be constructed by nearly the same algorithm. Furthermore, this paper also gives a general construction method for all instantaneously decodable RGR codes.

In this letter, blind adaptive H multiuser detection is developed by employing a generalized sidelobe canceler (GSC) with and without subweight partition scheme. It is shown that the adaptive H algorithm with subweight approach has the advantages of fast convergence speed, insensitivity of dynamic estimate error, and suitability for arbitrary ambient noise over the conventional H and the RLS-based adaptive algorithms.

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm2 in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.

Reactive sputtering of a metallic target in DC planar magnetron discharge shows a drastic mode transition between metallic and oxide modes. To describe the experimental results quantitatively, a new reactive sputtering model including the secondary electron emission coefficient of a target has been developed. The model is based on a simple reactive gas balance model proposed by Berg et al., and can quantitatively describe experimental results such as the oxygen flow rate dependence of deposition rate and discharge, observed for MgO sputter-deposition.

A multiport representation of the step junction of two circular dielectric waveguides of different size is given. Continuous spectral modes of the circular dielectric waveguide are discretized at a terminal plane by means of expressing their mode amplitudes in the form of infinite series of orthonormal Gaussian Laguerre function. Applying the mode matching technique, a multiport representation of the step junction is derived. Numerical examples are given where the results are tested for the conservation of power. Also the numerical results are compared with those from Marcuse's approximate methods.

We have manufactured a trial 'Digital Packet Video (PV) Link' system for super high-resolution display. 'Digital PV Link' is a new data transmission protocol where the host transfers video data with attributes for only a selected area such as a motion picture window. This protocol handles the video data with an ID, which can be used for handling between plural hosts and plural displays such as multi display. This ID also makes the display to handle plural windows in accordance with different parameter such as scaling factor, color-adjust, and so on. In this protocol, error handling is a key because the video data is transferred only when the host wants to change display data. So, we have examined transmission errors and capability for motion pictures by using this trial system. In this report, we will introduce the concept and the characteristics of 'Digital PV Link,' and the result of examination.

A plasma display panel (PDP) represents gray levels by the pulse number modulation technique that results in undesirable dynamic false contours on moving images. Among the various techniques proposed for the reduction of dynamic false contours, the optimization of the subfield pattern can be most easily implemented without the need for any additional dedicated hardware or software. In this paper, a systematic method for selecting the optimum subfield pattern is presented. In the proposed method, a subfield pattern that minimizes the quantitative measure of the dynamic false contour on the predefined test image is selected as the optimum pattern. The selection is made by repetitive calculations based on a genetic algorithm. Quantitative measure of the dynamic false contour calculated by simulation on the test image serves as a criterion for minimization by the genetic algorithm. In order to utilize the genetic algorithm, a structure of a string is proposed to satisfy the requirements for the subfield pattern. Also, three genetic operators for optimization, reproduction, crossover, and mutation, are specially designed for the selection of the optimum subfield pattern.

First, we give a graph-theoretic formalization for the spare assignment problems for two cases of reconfiguring NN mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numbers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faulty processors. The problem for the latter case, originally presented by Melhem, has already been discussed and solved by the O(N2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theoretic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases can be solved in O(N) time.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

Today software piracy is a major concern to electronic commerce since a digitized product such as software is vulnerable to redistribution and unauthorized use. This paper presents an enhanced electronic software distribution and software protection model. Authentication scheme of the proposed model is based on zero-knowledge (ZK) proof which requires limited computation. The proposed model considers post installation security using authentication agent. It prevents software piracy and illegal copy. It also provides secure and efficient software live-update mechanism based on traitor tracing scheme. Even if software or personal key is copied illegally, a merchant can trace back to its original owner from the electronic license and personal key. The proposed model provides security and reasonable performance and safety.

In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array can generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by an existing approach. We design our PLD based on a fundamental unit named nGCT cell which can be used as LUTs in multiple sizes or random access memories. Implementation of the PLD based on a fundamental unit named nGCT cell which can be used as LUTs or random access memories is also described.

A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a Single-Streaming Single Instruction, Multiple Data (SS-SIMD) architecture. To solve the code bloat problem which is common to VLIW architectures, the proposed method makes it possible to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the code compaction are compared to the SS-SIMD with the same instruction set and the same building blocks. The FP-VLIW shows the fastest speed performance in the evaluation results of the viewperf CDRS-03 benchmark programs. It is 36% faster than the SS-SIMD used as reference. The proposed compaction method keeps the 95% code density of the SS-SIMD. One test program shows that the code density of the MV-VLIW is higher than that of the SS-SIMD. This result demonstrates that the merit of compacting nops can be greater than the VLIW penalty. The FP-VLIW architecture with the code compaction achieves 1.36 times the speed performance without significant code-density deterioration.