Data mining is to analyze all the data in a huge database and to obtain useful information for database users. One of the well-studied problems in data mining is the search for meaningful association rules in a market basket database which contains massive amounts of sales transactions. The problem of mining meaningful association rules is to find all the large itemsets first, and then to construct meaningful association rules from the large itemsets. In our previous work, we have shown that it is NP-complete to decide whether there exists a large itemset with a given size. Also, we have proposed a subclass of databases, called k-sparse databases, for which we can efficiently find all the large itemsets. Intuitively, k-sparsity of a database means that the supports of itemsets of size k or more are sufficiently low in the database. In this paper, we introduce the notion of (k,c)-sparsity, which is strictly weaker than the k-sparsity in our previous work. The value of c represents a degree of sparsity. Using (k,c)-sparsity, we propose a larger subclass of databases for which we can still efficiently find all the large itemsets. Next, we propose alternative measures to the support. For each measure, an itemset is called highly co-occurrent if the value indicating the correlation among the items exceeds a given threshold. In this paper, we define the highly co-occurrent itemset problem formally as deciding whether there exists a highly co-occurrent itemset with a given size, and show that the problem is NP-complete under whichever measure. Furthermore, based on the notion of (k,c)-sparsity, we propose subclasses of databases for which we can efficiently find all the highly co-occurrent itemsets.

Spatio-temporal decorrelation is the task of eliminating correlations between associated signals in spatial domain as well as in time domain. In this paper, we present a simple but efficient adaptive algorithm for spatio-temporal decorrelation. For the task of spatio-temporal decorrelation, we consider a dynamic recurrent network and calculate the associated natural gradient for the minimization of an appropriate optimization function. The natural gradient based spatio-temporal decorrelation algorithm is applied to the task of blind deconvolution of linear single input multiple output (SIMO) system and its performance is compared to the spatio-temporal anti-Hebbian learning rule.

In this paper, we propose a method to minimize multiple-valued decision diagrams (MDDs) for multiple-output functions. We consider the following: (1) a heuristic for encoding the 2-valued inputs; and (2) a heuristic for ordering the multiple-valued input variables based on sampling, where each sample is a group of outputs. We first generate a 4-valued input 2-valued multiple-output function from the given 2-valued input 2-valued functions. Then, we construct an MDD for each sample and find a good variable ordering. Finally, we generate a variable ordering from the orderings of MDDs representing the samples, and minimize the entire MDDs. Experimental results show that the proposed method is much faster, and for many benchmark functions, it produces MDDs with fewer nodes than sifting. Especially, the proposed method generates much smaller MDDs in a short time for benchmark functions when several 2-valued input variables are grouped to form multiple-valued variables.

A real-time adaptive segmentation method based on new distance features is proposed for the binary centroid tracker. These novel features are distances between the predicted center pixel of a target object by a tracking filter and each pixel in extraction of a moving target. The proposed method restricts clutters with target-like intensity from entering a tracking window and has low computational complexity for real-time applications compared with other complex feature-based methods. Comparative experiments show that the proposed method is superior to other segmentation methods based on the intensity feature only in target detection and tracking.

In this study, we propose a simple multipoint-to-point ABR mechanism that can be implemented easily in existing ATM networks. The proposed scheme can provide fair bandwidth allocation among the sources in multipoint-to-point connection.

This paper describes two competitive learning algorithms from the viewpoint of deleting mechanisms of weight (reference) vectors. The techniques are termed the adaptivity and sensitivity deletions participated in the criteria of partition error and distortion error, respectively. Experimental results show the effectiveness of the proposed approaches in the average distortion.

A program is developed to simulate the signal received by a bistatic pulse radar for a defined scenario. The signal collected at the receiving antenna is calculated as a function of time by taking into account the vectorial aspect of the electromagnetic waves and various elements operating in the radar radiolink. The radar radiolink is designed in a modular structure for a general configuration where the transmitter, the target and the receiver are moving. Modules such as elements characterizing the antennas radiation or defining the target scattering can be inserted in accordance with the desired radar scenario. Then the developed model permits to simulate a wide range of radar scenarios where returns from targets and clutter can be individually processed and their characteristics can be investigated in time or frequency. The interest of this model is great because it permits, for a defined scenario, to generate radar data which can be used in signal processing algorithms for target detection, clutter suppression or target classification. This paper shows the implementation of the simulation program considering a concrete radar scenario. The presented scenario deals with the simulation of the sea clutter occurring in a bistatic radar radiolink over the sea surface. In this application where the sea surface is considered as the target, the electric field scattered from the sea surface is calculated by assuming that the surface is described by two independent scales of roughness.

In the beginning of the new century, many information appliance (IA) products will replace traditional electronic appliances to help people in smart, efficient, and low-cost ways. These successful products must be capable of communicating multimedia information, which is embedded into the electronic appliances with high integration, innovation, and power-throughput tradeoff. In this paper, we develop a codesign procedure to analyze, compare, and emulate the multimedia communication applications to find the candidate implementations under different criteria. The experimental results demonstrate that in general, memory technology dominates the optimal tradeoff and ALU improvements impact greatly on particular applications. The results also show that the proposed procedure is effective and quite efficient.

Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.

This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.

In this letter we propose a filter for extracting a quasi-periodic signal from a noisy observation using wavelets. It is assumed that the instantaneous frequency of the signal is known. A particularly difficult task when the frequency and amplitude of the desired signal are varying with time is shown. The proposed algorithm is compared with three other methods.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.

In this paper, the electromagnetic scattering from a cylinder with a computer-generated random rough surface is analyzed by a numerical simulation method. The validity of the proposed numerical method is confirmed by comparing the present numerical results with those calculated by the perturbation method to second order and its Pade approximation. It is shown that the present proposed method can be applied to the case where the surface roughness becomes relatively large.

Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (dEc) at the critical temperature. The WSSA uses a function (H(t)) that represents the probability for a hill-climbing with the dEc of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature t. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

In this paper, we present a new network design problem that is applicable for designing virtual paths (VP's) in an asynchronous transfer mode (ATM) network to efficiently support multicast applications, especially real-time multimedia applications. We first address several alternatives for the solution and compare their properties. Then we focus on a new solution which sets up a semi-permanent VP layout (VPL) and constructs VC trees for different multicast traffic demand patterns based on the constructed VPL. A three-phase heuristic solution is proposed for designing a good virtual-path layout for a given set of multicast traffic demand patterns. By varying the design parameters, we can obtain different VPLs which possess different tradeoffs among some important criteria, namely, the network overhead for a connection setup, routing table resources and control and management cost. Simulations are performed on randomly generated networks to demonstrate the performance and scalability of our solution. To the best of our knowledge, there is no prior known work which takes the multicast connection traffic into account for the VP layout design.

When a single-mode LD is subjected to distant reflection, relative intensity noise and the width of the optical spectrum are drastically increased. This phenomenon is known as 'coherence collapse. ' This letter demonstrates that penalty-free operation is possible at 2.5 Gbit/s even when a DFB-LD is in a state of coherence collapse. In addition, an LD in a state of coherence collapse is applied to a situation where signal light suffers from interferometric crosstalk. The results show that the LD reduces the influence of interferometric noise because of its wide spectral width.

A minimum classification error formulation based on genetic algorithm is proposed for discriminative training of the bigram language model. Results of Chinese dialect identification were reported which demonstrate performance improvement with use of the genetic algorithm over the generalized probabilistic descent algorithm.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using linear programming. In this algorithm, linear programming problems are formulated by surrounding component nonlinear functions by rectangles. In this letter, it is shown that weakly nonlinear functions can be surrounded by smaller rectangles, which makes the algorithm very efficient.

High-speed systems require a wide-frequency-range clock system for data processing. Phase-locked loop (PLL) is used for such a system that requires wide-range variable frequency clock. Frequency calibration method enables the voltage-controlled oscillator (VCO) in a PLL to cover the expected frequency range for high-speed applications that require a wide locking range. Frequency range adjustment is implemented by means of a current digital to analog converter (DAC), which controls the performance curves of a VCO and a bias circuit. This method adjusts the VCO's frequency-voltage performance curves before functional operation so that a PLL can cover requested frequency range with its best condition. Both the limit of control voltage and its target reference voltage are given with same voltage reference. This ensures correct performance after frequency adjustment even under the temperature fluctuation. It eliminates post-production physical adjustment such as fuse trimming which increases the cost and TAT in manufacturing and testing. A high-speed wide-locking range VCO with an automatic frequency performance calibration circuit is implemented within small space in a high-speed hard disk drive channel with 0.25-µm 2.5 V CMOS four-layer metal technology.