This paper presents a class of binary block codes capable of correcting single synchronization errors and single reversal errors with fewer check bits than the existing codes by 3 bits. This also shows a decoding circuit and analyzes its complexity.

Semantic ambiguity is a serious problem in information retrieval. Query expansion has been proposed as one method of solving this problem. However, queries tend not to have much information for fitting query vectors to the latent semantics, which are difficult to express in a few query terms given by users. We propose a document vector modification method that modifies document vectors based on the relevance of documents. This method is expected to show better retrieval effectiveness than conventional methods. In this paper, we evaluate our method through retrieval experiments in which the relevance of documents extracted from scientific papers is assessed, and a comparison with tfidf is described.

This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.

In this paper, we present a new network design problem that is applicable for designing virtual paths (VP's) in an asynchronous transfer mode (ATM) network to efficiently support multicast applications, especially real-time multimedia applications. We first address several alternatives for the solution and compare their properties. Then we focus on a new solution which sets up a semi-permanent VP layout (VPL) and constructs VC trees for different multicast traffic demand patterns based on the constructed VPL. A three-phase heuristic solution is proposed for designing a good virtual-path layout for a given set of multicast traffic demand patterns. By varying the design parameters, we can obtain different VPLs which possess different tradeoffs among some important criteria, namely, the network overhead for a connection setup, routing table resources and control and management cost. Simulations are performed on randomly generated networks to demonstrate the performance and scalability of our solution. To the best of our knowledge, there is no prior known work which takes the multicast connection traffic into account for the VP layout design.

Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (dEc) at the critical temperature. The WSSA uses a function (H(t)) that represents the probability for a hill-climbing with the dEc of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature t. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

The micro positioning systems using magnetic suspension technique, which is one of precision actuating method, have been suggested. Utilizing the various potentials such as the exclusion of a mechanical friction, they are being applied broadly to multi degrees of freedom (d.o.f) system requesting high accuracy or hybrid system requesting to be controlled position and force simultaneously. This paper presents the entire development procedure of a novel six d.o.f micro positioning system using mag-netic levitation, with a repulsive force mechanism covering the all d.o.f. First, the interactions between magnetic elements are modeled and the system design flow by an optimal location of the elements is given. A kinematic relationship between the measuring instruments and the levitated object is derived, and dynamic characteristics are identified by the narrow gap principles. And the main issues for control are discussed.

The power coupling coefficients between cores of waveguide systems with random geometrical imperfections along the fiber axis are determined by comparing numerical solutions of the coupled mode equations with numerical solutions of the coupled power equations and the dependence of the power coupling coefficient on the correlation length with respect to the propagation constants of modes is clarified. When the correlation length D is small the power coupling coefficient is proportional to κ 2 D where κ is the mean mode coupling coefficient and is independent of the fluctuation of the propagation constants. For sufficiently large D the power coupling coefficient dc decreases in proportion to D-1 with increasing D and when D , dc 0. Then the dependence of the power coupling coefficient on the mode coupling coefficient and the fluctuation of the propagation constants δ β is expressed as a function of a single variable κ /δ β .

This paper introduces a generalized cyclic convolution which can be implemented via the conventional cyclic convolution system by the discrete Fourier transform (DFT) with pre-multiplication for the input and post-multiplication for the output. The generalized cyclic convolution is applied for computing a negacyclic convolution. Comparison shows that the proposed implementation is more efficient and simpler in structure than other methods. The modified Fermat number transform (MFNT) is known to be useful for computing a linear convolution of integer-valued sequences. The generalized cyclic convolution is also applied for generalizing the linear convolution system by MFNT, and easing the signal length restriction imposed by the system.

A minimum classification error formulation based on genetic algorithm is proposed for discriminative training of the bigram language model. Results of Chinese dialect identification were reported which demonstrate performance improvement with use of the genetic algorithm over the generalized probabilistic descent algorithm.

This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

An Off-line mammography screening system is used in pre-screening mammograms to separate high-risk mammograms from most normal cases. Off-line system can run before radiologist's review and is particularly useful in the national breast cancer screening program which usually consists of high percentage of normal cases. Until now, the shortcomings of on-line detection of clustered microcalcifications from a mammogram remain in the necessity of manual selection of regions of interest. The developed technique focuses on detection of microcalcifications within a region of interest indicated by the radiologist. Therefore, this kind of system is not efficient enough to process hundreds of mammograms in a short time without a large number of radiologists. In this paper, based on a "hierarchically-coarse-to-fine" approach, an off-line mammography screening system for the detection and segmentation of clustered microcalcifications is presented. A serial off-line procedures without any human intervention should consider the complexity of organization of mammograms. In practice, it is impossible to use one technique to obtain clustered microcalcifications without consideration of background text and noises from image acquisition, the position of breast area and regions of interest. "Hierarchically-coarse-to-fine" approach is a serial procedures without any manual operations to reduce the potential areas of clustered microcalcifications from a mammogram until clustered microcalcifications are found. The reduction of potential areas starts with a mammogram, through identification of the breast area, identification of the suspicious areas of clustered microcalcifications, and finally segmentation of clustered microcalcifications. It is achieved hierarchically from coarse level to fine level. In detail, the proposed system includes breast area separation, enhancement, detection and localization of suspicious areas, segmentation of microcalcifications, and target selection of microcalcifications. The system separates its functions into hierarchical steps and follows the rule of thumb "coarse detection followed by fine segmentation" in performing each step of processing. The decomposed hierarchical steps are as follows: The system first extracts the breast region from which suspicious areas are detected. Then precise clustered microcalcification regions are segmented from the suspicious areas. For each step of operation, techniques for rough detection are first applied followed by a fine segmentation to accurately detect the boundaries of the target regions. With this "hierarchically-coarse-to-fine" approach, a complicated work such as the detection of clustered microcalcifications can be divided and conquered. The effectiveness of the system is evaluated by three experienced radiologists using two mammogram databases from the Nijmegen University Hospital and the Taichung Veterans General Hospital. Results indicate that the system can precisely extract the clustered microcalcifications without human intervention, and its performance is competitive with that of experienced radiologists, showing the system as a promising asset to radiologists.

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

In this paper, we propose a method to minimize multiple-valued decision diagrams (MDDs) for multiple-output functions. We consider the following: (1) a heuristic for encoding the 2-valued inputs; and (2) a heuristic for ordering the multiple-valued input variables based on sampling, where each sample is a group of outputs. We first generate a 4-valued input 2-valued multiple-output function from the given 2-valued input 2-valued functions. Then, we construct an MDD for each sample and find a good variable ordering. Finally, we generate a variable ordering from the orderings of MDDs representing the samples, and minimize the entire MDDs. Experimental results show that the proposed method is much faster, and for many benchmark functions, it produces MDDs with fewer nodes than sifting. Especially, the proposed method generates much smaller MDDs in a short time for benchmark functions when several 2-valued input variables are grouped to form multiple-valued variables.

This paper presents a new method that efficiently generates all of the kernels of a sum-of-products expression. Its main feature is the memorization of the kernel generation process by using a graph structure and implicit cube set representations. We also show its applications for common logic extraction. Our extraction method produces smaller circuits through several extensions than the extraction method based on two-cube divisors known as best ever.

CAM (Content Addressable Memory) units are generally designed so that they can be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application program written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.

Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.

In this letter we propose a filter for extracting a quasi-periodic signal from a noisy observation using wavelets. It is assumed that the instantaneous frequency of the signal is known. A particularly difficult task when the frequency and amplitude of the desired signal are varying with time is shown. The proposed algorithm is compared with three other methods.

Debye's asymptotic series is frequently used for calculation of cylindrical functions. However, it seems that until now this series has not been used in all-purpose programs for numerical calculation of the cylindrical functions. The authors attempt to develop these all-purpose programs. We present some improvements for the numerical calculation. As the results, Debye's series can be used for the all-purpose programs, and it is found out that the series gives sufficient accuracy if some conditions are satisfied.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.