This letter points out some flaws in the previous works on UKS (unknown key-share) attacks. We show that Blake-Wilson and Menezes' revised STS-MAC (Station-to-Station Message Authentication Code) protocol, which was proposed to prevent UKS attack, is still vulnerable to a new UKS attack. Also, Hirose and Yoshida's key agreement protocol presented at PKC'98 is shown to be insecure against public key substitution UKS attacks. Finally, we discuss countermeasures for such UKS attacks.

Recently, Plastic Cell Architecture (PCA) has been proposed as a hard-wired general-purpose autonomously reconfigurable processor. PCA consists of two layers, the plastic part on which sequential logic circuits are implemented, and the built-in part which induces the plastic part to dynamically reconfigure the circuits and transports messages among the circuits. The plastic part consists of an array of LUT-based reconfigurable logic primitives, each of which is connected only to adjacent ones. Combining logic and layout synthesis, we propose a new array-based algorithm to map logic functions into the PCA plastic part. This algorithm produces a folded array of sum-of-multi-input-complex-terms, especially for the PCA plastic part.

This letter presents an adaptive beamforming algorithm for an MC-CDMA system with adaptive antenna array. The proposed adaptive beamforming algorithm for the MC-CDMA systems is derived by (1) calculating the error signals between the pilot symbols of desired user and the received pilot signals in the frequency-domain, (2) transforming the frequency-domain error signals into time-domain error signals, (3) updating the filter coefficients of the adaptive beamformer in the direction of minimizing the MSE. Convergence behavior and user-capacity improvement of the proposed approach are demonstrated through computer simulation by applying it to the MC-CDMA system in the presence of interferences from other users.

In the beginning of the new century, many information appliance (IA) products will replace traditional electronic appliances to help people in smart, efficient, and low-cost ways. These successful products must be capable of communicating multimedia information, which is embedded into the electronic appliances with high integration, innovation, and power-throughput tradeoff. In this paper, we develop a codesign procedure to analyze, compare, and emulate the multimedia communication applications to find the candidate implementations under different criteria. The experimental results demonstrate that in general, memory technology dominates the optimal tradeoff and ALU improvements impact greatly on particular applications. The results also show that the proposed procedure is effective and quite efficient.

The signed regressor algorithm, a variation of the least mean square (LMS) algorithm, is characterized by the estimation way of using the clipped reference signals, namely, its sign (). This clipping, equivalent to quantizing the reference signal to 1, only increases the estimation error by about 2 dB. This paper proposes to increase the number of the quantization steps to three, namely, 1 and 0, and shows that the 'tri-quantized-x' normalized least mean square (NLMS) algorithm with three quantization steps improves the convergence property.

In reliable multicast communications, retransmission control plays an important role from the viewpoint of scalability. Previous works show that the implosion of control packets, e.g. ACKs or NAKs, degrades the total performance of reliable multicast communications. Local recovery which enables receivers receiving a packet successfully to initiate recovering a lost packet may have the possibility to solve this scalability problem. This paper presents the performance evaluation of local recovery caused by grouping receiving nodes in reliable multicast communication. There seems to be many features dominating the performance of local recovery, the number of nodes in a group, the shared loss occurring simultaneously at multiple receivers and so on. When the number of receivers in a group increases, the geographical expansion of a group will degrade the delay performance of the receivers. In a configuration where most nodes in a local-recovery group suffer from shared loss, the failure of local recovery degrades the total performance. Our simulation results under a hierarchical network topology like the real Internet show that a local-recovery group configuration with two-adjacent MANs grouping performs well.

This paper introduces a flexible, stream-oriented dataflow processing model based on the "Communicating Logic (CL)" framework. As the target architecture, we adopt the dual layered "Plastic Cell Architecture (PCA). " Datapath processing functionality is encapsulated in asynchronous hardware objects with variable graining and implemented using look-up tables. Communication (i.e. connectivity and control) between the distributed processing objects is achieved by means of inter-object message passing. The key point of the CL approach is that it offers the merits of scalable performance, low power hardware implementation with the user friendly compilation and linking capabilities unique to software.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

Precise simulation of non-quasi-static (NQS) characteristics is crucial for the analog application of MOS transistors. This paper presents the small signal admittance model of four-terminal NQS MOS transistors by solving the differential equation derived from the primary principle. The model contains the bulk-charge effect, the mobility reduction, and the velocity saturation. The results are compared with those for the conventional quasi-static model, the BSIM3v3 NQS model, and the 2-D device simulation.

In this paper we develop a robust control theory to achieve fault-tolerant behaviors of timed discrete event systems (DESs) with model uncertainty represented as a set of some possible models. To demonstrate the effectiveness of the proposed theory, we provide a case study of a resistance spot welding process.

A minimum classification error formulation based on genetic algorithm is proposed for discriminative training of the bigram language model. Results of Chinese dialect identification were reported which demonstrate performance improvement with use of the genetic algorithm over the generalized probabilistic descent algorithm.

High-speed systems require a wide-frequency-range clock system for data processing. Phase-locked loop (PLL) is used for such a system that requires wide-range variable frequency clock. Frequency calibration method enables the voltage-controlled oscillator (VCO) in a PLL to cover the expected frequency range for high-speed applications that require a wide locking range. Frequency range adjustment is implemented by means of a current digital to analog converter (DAC), which controls the performance curves of a VCO and a bias circuit. This method adjusts the VCO's frequency-voltage performance curves before functional operation so that a PLL can cover requested frequency range with its best condition. Both the limit of control voltage and its target reference voltage are given with same voltage reference. This ensures correct performance after frequency adjustment even under the temperature fluctuation. It eliminates post-production physical adjustment such as fuse trimming which increases the cost and TAT in manufacturing and testing. A high-speed wide-locking range VCO with an automatic frequency performance calibration circuit is implemented within small space in a high-speed hard disk drive channel with 0.25-µm 2.5 V CMOS four-layer metal technology.

Methods for implementing SS7 functions are proposed for a large-capacity decentralized switching node; they satisfy the condition of hiding distributed configurations from adjacent nodes. First, line accommodation and acquisition methods are clarified for a large-capacity switching node in which multiple modules are used to realize trunk circuits and SS7 signaling links. Two methods are then proposed for allocating SS7 functions within the switching node. One distributes the functions over multiple circuit-switched modules (distributed allocation) while the other centralizes the functions in dedicated signaling modules (centralized allocation). We quantitatively evaluate both methods in terms of node scale versus the number of modules and signaling links required, the inter-module data transfer rate required, and the node traffic handling capacity when a particular module fails. From the evaluation results, we show that the distributed allocation should be employed for small-scale nodes and the centralized allocation for large-scale nodes. We also show the effectiveness of a method for avoiding a characteristic problem that arises when a particular module fails. Finally, we implement an experimental system as an example.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using linear programming. In this algorithm, linear programming problems are formulated by surrounding component nonlinear functions by rectangles. In this letter, it is shown that weakly nonlinear functions can be surrounded by smaller rectangles, which makes the algorithm very efficient.

DC-free error-correcting codes based on partition chain are presented in this paper. The partition chain can be constructed from code partition chain of Reed-Muller codes. The line coding parameters for the partition chain such as maximum runlength and running digital sum are obtained. The trellis and multilevel code structure can be used to design the DC-free error-correcting codes. Especially, by adopting DC-free trellis codes as constituent codes, DC-free turbo codes can be designed. As results, the presented DC-free error-correcting codes have good coding characteristics.

We study the electromagnetic wave propagation in three-dimensional (3-D) dense random discrete media containing dielectric spheroidal scatterers. We employ a Monte Carlo method in conjunction with the Method of Moments to solve the volume integral equation for the electric field. We calculate the effective permittivity of the random medium through a coherent-field approach and compare our results with a classical mixing formula. A parametric study on the dependence of the effective permittivity on particle elongation and fractional volume is included.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

In designing a field-programmable gate array (FPGA)-based processor for motion stereo, a parallel memory system and a simple interconnection network for parallel data transfer are essential for parallel image processing. This paper, firstly, presents an FPGA-oriented hierarchical memory system. To reduce the bandwidth requirement between an on-chip memory in an FPGA and external memories, we propose an efficient scheduling: Once pixels are transferred to the on-chip memory, operations associated with the data are consecutively performed. Secondly, a rectangular memory allocation is proposed which allocates pixels to be accessed in parallel onto different memory modules of the on-chip memory. Consequently, completely parallel access can be achieved. The memory allocation also minimizes the required capacity of the on-chip memory and thus is suitable for FPGA-based implementation. Finally, a functional unit allocation is proposed to minimize the complexity between memory modules and functional units. An experimental result shows that the performance of the processor becomes 96 times higher than that of a 400 MHz Pentium II.

Two new algorithms for improving the speed of the LZ77 compression are proposed. One is based on a new hashing algorithm named two-level hashing that enables fast longest match searching from a sliding dictionary, and the other uses suffix sorting. The former is suitable for small dictionaries and it significantly improves the speed of gzip, which uses a naive hashing algorithm. The latter is suitable for large dictionaries which improve compression ratio for large files. We also experiment on the compression ratio and the speed of block sorting compression, which uses suffix sorting in its compression algorithm. The results show that the LZ77 using the two-level hash is suitable for small dictionaries, the LZ77 using suffix sorting is good for large dictionaries when fast decompression speed and efficient use of memory are necessary, and block sorting is good for large dictionaries.

Spatio-temporal decorrelation is the task of eliminating correlations between associated signals in spatial domain as well as in time domain. In this paper, we present a simple but efficient adaptive algorithm for spatio-temporal decorrelation. For the task of spatio-temporal decorrelation, we consider a dynamic recurrent network and calculate the associated natural gradient for the minimization of an appropriate optimization function. The natural gradient based spatio-temporal decorrelation algorithm is applied to the task of blind deconvolution of linear single input multiple output (SIMO) system and its performance is compared to the spatio-temporal anti-Hebbian learning rule.