It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

The present study describes using the state transition type of drawing understanding framework to construct a multi-purpose drawing understanding system. This new system employs an understanding process that complies with the understanding rules, which are easily obtained by the user. The same set of user-provided rules must be used for the same type of target drawings, but for slightly different ones, fine tuning is required to obtain understanding rules. To overcome this inherent drawback in constructing drawing understanding systems, we extended the system using a newly constructed understanding rule generating support system. The resultant integrated system is based on a man-machine cooperation type interface, and can automatically generate rules from user-provided simple interactions using a graphical user interace (GUI). To obtain efficient rule generation, the system employs an inductive inference method as a learning algorithm. Map-drawing experiments were successfully carried out, and an evaluation based on a rule leaning error criterion subsequently revealed an efficient rule generation process.

In this paper, authors discuss on a lexicon directed algorithm for recognition of unconstrained handwritten words (cursive, discrete, or mixed) such as those encountered in mail pieces. The procedure consists of binarization, presegmentation, intermediate feature extraction, segmentation recognition, and post-processing. The segmentation recognition and the post-processing are repeated for all lexicon words while the binarization to the intermediate feature extraction are applied once for an input word. This algorithm is essentially non hierarchical in character segmentation and recognition which are performed in a single segmentation recognition process. The result of performance evaluation using large handwritten address block database, and algorithm improvements are described and discussed to achieve higher recognition accuracy and speed. Experimental studies with about 3000 word images indicate that overall accuracy in the range of 91% to 98% depending on the size of the lexicon (assumed to contain correct word) are achievable with the processing speed of 20 to 30 word per minute on typical work station.

A method for extracting and recognizing character strings from unformed document images, which have inclined character strings and have no structure at all, is described. To process such kinds of unformed documents, previous schemes, which are intended only to deal with documents containing nothing but horizontal or vertical strings of characters, do not work well. Our method is based on the idea that the processes of recognition and extraction of character patterns should operate together, and on the characteristic that the character patterns are located close to each other when they belong to the same string. The method has been implemented and applied to several images. The experimental results show the robustness of our method.

A new design method for 2-D IIR digital filters, having a separable denominator,in the spatial domain is presented. The modified Gauss Method is applied in the iterating calculation of the filter coefficients. Also, the 1-D state space representation of the denominator is utilized in determining the impulse response of the designed IIR transfer function and its partial derivatives systematically while the numerator is expressed by a nonseparable polynomial. The error criterion function, which also includes the response outside the given region of support, is minimized in the least square sense. Convergence, together with the stability of the resulting filttr, are guaranteed.

This paper presents an algorithm for string searching in a character lattice. A character lattice, which is obtained through a character recognition process, is a general and flexible data structure that represents many hypothesized strings in a document image. In this paper, the authors propose a simple and efficient algorithm; it consists of a single loop of some set-operations and scans the character lattice only once. The authors also describe two actual implementations of the algorithm; one uses Bit-Arrays and the other a Trie. Owing to its bir parallelism, the Bit-Array approach is able to search for a single pattern faster than the Trie approach, and is easily extended to complex matchings such as an approximate one. It is suited for document retrieval systems that need to search for a keyword as fast as possible. A hashed compact version of the character lattice is also useful to increase the speed of the search for a single pattern. In contrast, the Trie approach is able to search for a large number of patterns simultaneously, and is suited for document understanding systems that need to extract words from the character lattice. The experimental results have shown that both approaches achieve high performance.

This paper reviews two topics of nonlinear system analysis done in Japan. The first half of this paper concerns with nonlinear system analysis through the nondeterministic operator theory. The nondeterministic operator is a set-valued or fuzzy set valued operator by K. Horiuchi. From 1975 Horiuchi has developed fixed point theorems for nondeterministic operators. Using such fixed point theorems, he developed a unique theory for nonlinear system analysis. Horiuchi's theory provides a fundamental view point for analysis of fluctuations in nonlinear systems. In this paper, it is pointed out that Horiuchi's theory can be viewed as an extension of the interval analysis. Next, Urabe's theory for nonlinear boundary value problems is discussed. From 1965 Urabe has developed a method of computer assisted existence proof for solutions of nonlinear boundary value problems. Urabe has presented a convergence theorem for a certain simplified Newton method. Urabe's theorem is essentially based on Banach's contraction mapping theorem. In this paper, reformulation of Urabe's theory using the interval analysis is presented. It is shown that sharp error estimation can be obtained by this reformulation. Both works discussed in this paper have been done independently with the interval analysis. This paper points out that they have deep relationship with the interval analysis. Moreover, it is also pointed out that these two works suggest future directions of the interval analysis.

We study robot navigation in unknown environment with rectangular obstacles aligned with the x and y axes. We propose a strategy called the modified-bian heuristic, and analyze its efficiency. Let n be the distance between the start point and the target of robot navigation, and let k be the maximum side length among the obstacles in a scene. We show that if k=(o(n) and if the summation of the widths of the obstacles on the line crossing the target and along the y axis is o(n), then ratio of the total distance walked by the robot to the shortest path length between the start point and the target is at most arbitrarily close to 1+k/2, as n grows. For the same restrictions as above on the sizes of the obstacles, the ratio is also at most arbitrarily close to 1+3/4n, as n grows, where is the summation of lengths of the obstacles in y axis direction.

An efficient algorithm is presented for solving nonlinear resistive networks. In this algorithm, the techniques of the piecewise-linear homotopy method are introduced to the Katzenelson algorithm, which is known to be globally convergent for a broad class of piecewise-linear resistive networks. The proposed algorithm has the following advantages over the original Katzenelson algorithm. First, it can be applied directly to nonlinear (not piecewise-linear) network equations. Secondly, it can find the accurate solutions of the nonlinear network equations with quadratic convergence. Therefore, accurate solutions can be computed efficiently without the piecewise-linear modeling process. The proposed algorithm is practically more advantageous than the piecewise-linear homotopy method because it is based on the Katzenelson algorithm that is very popular in circuit simulation and has been implemented on several circuit simulators.

This paper proposes a semi-autonomous frame synchronization scheme for a TDMA (Time Division Multiple Access)-TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization in a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame timing control, and compensates the propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation and analysis results confirm the accurate and stable TDMA frame synchronization of all base stations even in fading environments.

A fuzzy microprocessor is developed using 1.2 µm CMOS process. The inference scheme for the if-then fuzzy rules consists of three main steps i. e. if-part process, then-part process and defuzzification. In order to realize very high-speed inference and moderate programmability, we introduce three-type different structures i.e. SIMD, logic-in-memory and Wallace tree structures which are suitable for the three main steps. The inference speed including defuzzification is 7.5 MFLIPS which is 12.9 times higher than the previous VLSI implementation, and it can carry out many rules (960 rules) and many input and output variables (16 variables).

A new frequency hopped spread spectrum system is introduced. The frequency hopped signal is a combination of multi frequency and multi phase signals and is referred to as Frequency Hopped/Joint Frequency-Phase Modulation (FH/JFPM). A noncoherent receiver for the FH/JFPM signals is introduced and an exact expression for the bit error rate is obtained. A performance analysis of this system is given in the presence of broadband and partial-band noise jamming. The optimal jamming strategy is evaluated. The results show that under these jamming conditions the FH/JFPM perform better than the FH/M-ary DPSK and FH/M-ary FSK systems. It is also shown that for a given channel bandwidth and data rate, the FH/JFPM system has more processing gain than its FSK or DPSK counterparts.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

Personal Handy Phone (PHP), the Japanese digital cordless telephone system is being developed. The 32kbits/s ADPCM (Adaptive Differential Pulse Code Modulation) codec has been standardized for PHP. This paper describes firstly, the advanced algorithms of a Voice Activity Detection (VAD) function that reduces power dissipation of a digital cordless telephone terminal, secondly, a comfort noise generator operates in conjunction with the VAD and finally, a transmission error control based on the use of the prediction coefficients generated in the ADPCM codec. These proposed algorithms function in the low signal-to-noise ratio (SNR) environment of personal radio communications. The quality of the reconstructed speech after the process is influenced by the VAD decision errors (false detection when no voice is present, or no detection when voice is present) , the similarity of the generated comfort noise to the actual background noise, and the transmission quality. The simulation results of the performance achieved by these algorithms are shown and required loading of the computation are also given.

In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.

In this paper we propose a method for increasing the reliability in multiprocessor realization of lowpass and highpass FIR digital filters possessing a maximally flat magnitude response. This method is based on the use of array realization of the filter which has been proposed earlier by the authors. It is shown that if a processing module of the array functions erroneously, it is possible to exclude the module and still obtain a lowpass FIR filter. However, as a price we should tolerate a slight degradation in the magnitude response of the filter that is equivalent to a wider transition band. We also analyze the behavior of the filter when our proposed schemes are implemented on more than one module. The justification of our approach is based on that a slight degradation of the spectral characteristics of a filter may be well tolerated in most filtering applications and thus a graceful degradation in the frequency domain can sufficiently reduce the vulnerability to errors.

Wide-band, low-ripple underwater transducers with high-power acoustic radiation capability have been designed on the basis of multiple-mode filter synthesis theory. They are composed of triple acoustic matching plates and double backing plates with optimized specific acoustic impedances,besides piezoelectric ceramic elements. One of the backing plates employs a Fe damping-alloy to suppress unwanted response peaks in the frequency range above the passband region. Two 33 array transducers were fabricated, each with a center frequency of 200 kHz, one as a transmitter and the other as a receiver. The two transducers show high-sensitivity, low-ripple and wide-band transmitting and receiving responses. Then, the transducers were applied in a color video picture digital transmission system.Clear color video pictures, composed of 256240 pixels, were successfully received within one second.

This paper shows that when a pattern matching method used in optical character readers is highly accurate, it can be used effectively in on-line Japanese character recognition. Stroke matching methods used in previous conventional on-line character recognition have restricted the number and the order of strokes. On the other hand, orientation-feature pattern matching methods avoid these restrictions. The authors have improved a pattern matching method with the development in the flexible pattern matching (FPM) method, based on nonlinear shape normalization and nonlinear pattern matching, which includes the normalization-cooperative feature extraction (NCFE) method. These improvements have increased the recognition rate from 81.9% to 95.9%, when applied to the off-line database ETL-9 from the Electrotechnical Laboratory, Japan. When applied on-line to the examination of 151,533 Kanji and Hiragana characters in 3,036 categories, the recognition rate achieved 94.0%, while the cumulative recognition rate within the best ten candidates was 99.1%.

An analog circuit is devised which selects and outputs the kth largest element among n input voltages. The circuit is composed of n basic transconductance amplifiers connected mutually with an O(n) length wire, thus the complexity of the circuit is O(n). The circuit becomes particularly simple for the case of the selection of the median of inputs.

An adaptive LMS filtering system is proposed for computing the Discrete Walsh Transform (DWT). The signal to be transformed serves as the 'desired signal' for the adaptive filter, while a set of periodic Walsh sequences serve as the input signal vector for the adaptive filter. The weights of the adaptive filter provide the DWT. The given approach is more efficient in terms of the required computations and memory locations compared with the direct approach. In contract with existing Fast DWT algorithm, the proposed solution provides more flexibility as far as the signal block length is concerned. In other words, the proposed approach is not restricted to a block length N to be of power 2.