Since electromagnetic (EM) noise resulting from an arc discharge disturbs other electric devices, parameters on electromagnetic compatibility, as well as lifetime and reliability, are important properties for electrical contacts. To clarify the characteristics and the mechanism of the generation of the EM noise, the arc column and voltage fluctuations generated by slowly breaking contacts with external direct current (DC) magnetic field, up to 20,mT, was investigated experimentally using Ag$_{90.7{ m wt%}}$SnO$_{2,9.3{ m wt}%}$ material. Firstly the motion of the arc column is measured by high-speed camera. Secondary, the distribution of the motion of the arc and contact voltage are discussed. It was revealed that the contact voltage fluctuation in the arc duration is related to the arc column motion.

The circuit switching device by the electrical contact needs the high reliability and long lifetime. The very important factor for the high reliability, long lifetime and electromagnetic noise of the electrical contact is to suppress the duration and electromagnetic noise of arc discharge. Usually, the suppression of arc duration method is applying the external magnetic field. But, this method was not able to suppress the metallic arc duration and increased the voltage fluctuation at arc duration. Therefore, the new method for suppressing the duration and noise for electrical contact is expected. In this paper, a new method for suppressing duration and EM noise of arc discharge by applying housing pressure is proposed. To investigate the availability of proposed method, the measurement and some considerations on arc duration, voltage-fluctuation and current noise up to GHz frequency band generated by breaking contact in the applied pressure relay housing are reported. Firstly, voltage waveform and duration of the arc are measured. The effects of the pressure in the relay housing on the duration of the metallic and gaseous phase arcs are discussed. Secondary, voltage fluctuation, the spectrogram of contact voltage and current noise up to GHz frequency band are discussed. In the results, the proposed method with applying pressure makes shorter both durations of metallic and gaseous phases. The shorter duration of metallic phase is an advantage of the proposed method beyond the applying external magnetic field. As the housing pressure is increase, the voltage fluctuation and current noise becomes smalls. The proposed method can suppress the voltage fluctuation as well as arc duration. Consequently, the proposed method is on of the good solution to suppress the duration and electromagnetic noise of the arc discharge from electrical contact and result of this study indicates the basic considerations necessary to ensure good lifetime and EMC designs for electrical contacts.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate Vt fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.

This paper describes how voltage fluctuation in the DC power supply of a digital IC can be reduced, by means of molding the package-pin in a ferrite-resin composite. The voltage fluctuation of the DC power supply, when the input terminal was driven by a 40 MHz, 5 Vp-p pulse wave, was measured using an oscilloscope. Simultaneously, the voltage spectrum of the fluctuation was measured using a spectrum analyzer. As a result, the voltage fluctuation was decreased by about 50 % when the IC package-pins were molded in a ferrite-resin composite, in which the µiac of the ferrite powder equalled 100, and the powder content was 80 weight-%. In the same IC, there was the reduction effect of the voltage spectrum of the fluctuation was recognized in the frequency range 40 MHz to 1 GHz.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.

The electromagnetic interference (EMI) induced by steady arc has been demonstrated to be dependent on arc voltage fluctuation when the arc transfers from the metallic phase to the gaseous phase. In order to give the physical understanding of this arc voltage fluctuation and EMI, several typical materials, such as Ag, Cu and Zr, were tested and their arc behavior was determined and compared. The experimental results indicated that the arc behavior, in particular the arc voltage fluctuation in the moment that metallic phase transfers to the gaseous phase was different for different materials. Based on the test results and former investigations, a plausible mechanism is proposed for understanding these phenomena.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.