In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

Location theory on networks is concerned with the problem of selecting the best location in a specified network for facilities. Many studies for the theory have been done. We have studied location theory from the standpoint of measuring the closeness between two vertices by the capacity (maximum flow value) between two vertices. In a previous paper, we have considered location problems, called covering problems and proposed polynomial time algorithms for these problems. These problems are applicable to assigning files to some computers in a computer network. This paper is concerned with a covering problem called the single cover problem defined in the previous paper. First, we define a generalized single cover problem and show that an algorithm proposed in the previous paper can be applicable to solving the generalized single cover problem. Then, we define a single cover problem satisfying cardinality constrains and show that the problem is solved in a polynomial time.

For L 2, M 8, and transmission rate R = (log2M-1) bit/sym, a method for constructing GU trellis codes with L MPSK constellations is proposed and it is shown that the maximally achievable free distance is twice larger than it was previously reported for GU codes. Basides being geometrically uniform, these codes perform as good as Pietrobon's non-GU trellis codes with multidimensional MPSK constellations.

We propose two multipriority reservation protocols for wavelength division multiplexing (WDM) networks. The network architecture is a single-hop with control channel-based passive star topology. Each station is equipped with two pairs of laser and filter. One pair of laser and filter is always tuned to wavelength λ0 for control and the other pair of laser and filter can be tuned to any of data wavelengths, λ1, λ2, ..., λN. According to the access methods of the control channel, one protocol is called slotted ALOHA-based protocol and the other protocol is called TDM-based protocol. The two protocols have the following properties. First, each of them has its own priority control scheme which easily accommodates multipriority traffics. Second, they can be employed in the network with limited channels, i.e. the number of stations in the system is not restricted by the number of data channels. Third, they are conflict-free protocols. By using a reservation scheme and a distributed arbitration algorithm, channel collision and destination conflict can be avoided. For the performance point of view, the TDM-based protocol gives an optimal solution for the priority control. However it is less scalable than the slotted ALOHA-based protocol. The slotted ALOHA-based protocol also performs good priority control even though it is not an optimal solution. We analyze their performances using a discrete time Markov model and verify the results by simulation.

The designed converter has a two-input-winding transformer powered by single-phase AC voltage and an energy storage capacitor. Small size and enhanced conversion efficiency are achieved, because more than half of the energy is supplied to the load via a single conversion stage, and fast output-voltage regulation is achieved by controlling the charging and discharging of the storage capacitor. The design and control methods for the converter take into account the reset conditions of the transformer and stability in the output voltage control. An almost unity power factor and a low output voltage ripple were achieved with this converter fabricated as a breadboard circuit using small capacitors.

The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self-timed design technique, based on the Muller model, improves performance by eliminating the global clock. In order to prevent hazard, a self-timed system should satisfy certain assumptions and timing constraints, therefore special cells are required. The novel Self-timed Cell Library is designed for 1.2µm CMOS technology which contains Muller C-elements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provides a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog simulator; (3) It is flexible since it is compatible with an existing Standard Cell Library. In this paper, the library is described. Moreover, the simulated and measured cell characteristics are compared. Using the library, two [18] [81] matrix multipliers employing (1) DCVSL technique, and (2) micropipeline technique have been implemented as design examples and the results are compared. In addition, this paper also demonstrates the benefits of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also proposed.

Let L be any class of languages, L' be a class of languages which is closed under λ-free homomorphisms, and Σ be any alphabet. In this paper, we show that if the following statement (1) holds, then the statement (2) holds. (1) For any language L in L over Σ, there exist an alphabet of k pairs of matching parentheses Xk, Dyck reduction Red over Xk, and a language L1 in L' over ΣXk such that L=Red(L1)Σ*. (2) For any language L in L over Σ, there exist an alphabet Γ including Σ, a homomorphism h : Γ*Σ*, a Dyck language D over Γ, and a language L2 in L' over Γ such that L=h(DL2). We also give an application of this result.

In this paper, we give a concrete example of a 10-bit video rate ADC and introduce the effect of top-down design methodology with analog-HDL from the viewpoint of utilization techniques. First, we explain that analog top-down design methodology can improve chip performance by optimizing the architecture. Next, we concretely discuss the importance of modeling and verification. Verification of the full system does not require extracting all the information for each block at the transistor level in detail. The flexible verification method that we propose can provide good and fast full chip verification. We think analog top-down disign methodology will become increasingly more important from now on because "system-on-chip" requires one chip mixed-signal system LSIs.

This paper studies stabilization of timed discrete event systems with forcible events. We present an algorithm for computing the region of weak attraction for legal states.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

Superposed ATM cell streams have burstiness and strong autocorrelation properties. This paper investigates traffic measurement-based modeling method for superposed ATM cell streams. We develop a new measurement method based on monitoring both the waiting time distribution in a monitoring queue and the autocorrelation of cell interarrival times. Through the monitoring queue, we directly observe the queueing effect of superposed cell flows on ATM multiplexers. The measured traffic is modeled as the two-state MMPP. With the measured traffic, we estimate the cell loss probability in ATM multiplexers from the MMPP/D/1/K queue. Our method successfully works with homogeneous and heterogeneous superposition of traffic sources including voice, data, and video. These results can be applied to the evaluation of ATM multiplexers, traffic engineering, and network performance monitoring.

The applicability of a boundary matching technique is presented for reconstructing the refractive-index profile of a circularly symmetric cylinder from the measurement of the scattered wave when the cylinder is illuminated by an H-polarized plane wave. The algorithm of reconstruction is based on an iterative procedure of matching the scattered wave calculated from a certain refractive-index distribution with the measured scattered-wave. The limits of reconstruction for strongly inhomogeneous lossless and lossy cylinders are numerically shown through computer simulations under noisy environment, and are compared with those in the E-wave case.

Periodic solutions of slow-fast systems called "canards," "ducks," or "lost solutions" are examined in a second order autonomous system. A characteristic feature of the canard is that the solution very slowly moves along the negative resistance of the slow curve. This feature comes from that the solution moves on or very close to a curve which is called slow manifolds or "rivers." To say reversely, solutions which move very close to the river are canards, this gives a heuristic definition of the canard. In this paper, the generation mechanism of the canard is examined using a piecewise linear system in which the cubic function is replaced by piecewise linear functions with three or four segments. Firstly, we pick out the rough characteristic feature of the vector field of the original nonlinear system with the cubic function. Then, using a piecewise linear model with three segments, it is shown that the slow manifold corresponding to the less eigenvalue of two positive real ones is the river in the segment which has the negative resistance. However, it is also shown that canards are never generated in the three segments piecewise linear model because of the existence of the "nodal type" invariant manifolds in the segment. In order to generate the canard, we propose a four segments piecewise linear model in which the property of the equilibrium point is an unstable focus.

A 2.4 GHz band direct sequence (DS) spread spectrum (SS) radio frequency modem with a wide bandwidth of 26 MHz in half-duplex system has been newly developed using the small size (832 mm) and highly-efficient (-57 dBm) elastic type of surface acoustic wave (SAW) convolver. The size of SS modem is 905011 mm and the weight is 75 g. The power consumption of SS modem is 1.5 W and data rate is 206 kbps with 63 chips of PN code. Electrical characteristics measurements were made to evaluate the SS modem performance.

We apply a novel methodology, based on statecharts, to the design of large scale asynchronous systems. The design is specified at multiple levels, simulated, animated, and compiled into synthesizable VHDL code by using the ExpressV-HDL CAD tool. We add a validation sub-system to chech correct operation. ExpressV-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependence on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronous circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.

Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

The currying of term rewriting systems (TRSs) is a transformation of TRSs from a functional form to an applicative form. We have already introduced an order-sorted version of currying and proved that the compatibility and confluence of order-sorted TRSs were preserved by currying. In this paper, we focus on a key property of TRSs, completeness. We first show some proofs omitted in Ref. [3]. Then, we prove that the SN (strongly normalizing) property, which corresponds to termination of a program, is preserved by currying. Finally, we prove that the completeness of compatible order-sorted TRSs is preserved by currying.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

Fiber physical contact (FPC) is proposed and demonstrated as a new method designed to enable fibers to be connected easily with a small structure while maintaining high optical performance. FPC is performed by mating two bare optical fibers in a micro sleeve and fixing them to a holder while they are buckled. Buckling is a phenomenon whereby a long column is bent by compression along its length. PC connection is realized by the buckling force of the fibers themselves and does not require any springs. Optical fiber buckling is studied both theoretically and experimentally. The buckling force, which is determined by an initial span between the optical fiber holding points, remains constant when the span is changed and is useful as the PC force. The buckling amplitude which is determined by the span reduction must be so small that it does not cause excess radiation loss. A suitable span is about 7 mm. This generates a 0.7 N. The allowed span reduction is 0.1 mm. This results in a buckling amplitude of 0.64 mm which prevents radiation losses of above 0.1 dB for 1.31 µm light. Based on a study of fiber buckling, we demonstrate the optical performance for FPC connection with a 0.126 mm diameter micro sleeve in which optical fibers are mated and with polished fiber end faces. The insertion loss is under 0.3 dB and the average return loss is 50 dB for 1.31 µm light. These values are stable in the 20 to 70 temperature range. We confirm that FPC connection realizes high optical performance with a small simple structure.