We propose a memory-based processor called a Functional Memory Type Parallel Processor for vector quantization (FMPP-VQ). The FMPP-VQ is intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search on vector quantization. In the nearest neighbor search, we look for a vector nearest to an input one among a large number of code vectors. The FMPP-VQ has as many PEs (processing elements, also called "blocks") as code vectors. Thus distances between an input vector and code vectors are computed simultaneously in every PE. The minimum value of all the distances is searched in parallel, as in conventional CAMs. The computation time does not depend on the number of code vectors. In this paper, we explain the detail of the architecture of the FMPP-VQ, its performance and its layout density. We designed and fabricated an LSI including four PEs. The test results and performance estimation of the LSI are also reported.

Macro/microcellular systems have recently been proposed to accommodate both fast and slow moving users. If macrocells and microcells reuse the same frequency band in a macro/microcellular system, the interference between both types of cells can become a critical problem and degrade system capacity, particularly in CDMA systems. In this paper, Frequency Division CDMA (FD-CDMA) is applied to CDMA macro/spot-microcellular systems and uplink capacity is evaluated. The CDMA frequency band is divided into several subbands and both macrocells and microcells reuse the same subbands simultaneously. Interference signals from both types of cells are dispersed by dividing the frequency band, and performance degradation resulting from interference is reduced at both the macrocell and microcell. By reusing the same frequency band for macrocells and microcells, the system capacities become more flexible and can be changed according to variations in traffic. This paper describes the detail of the FD-CDMA system. Uplink capacities are calculated for some cell conditions such as microcell size or location through simulation evaluations. A comparison with a non-reuse subband system as well as results of adaptive control of subbands are described.

A new configuration of high gain circularly polarized microstrip antenna with a diagonal short and its analysis using boundary element method with a radiation load are presented. The center of a radiating patch is shorted with a 45-degree diagonal offset for not only obtaining a high gain but exciting a circular polarization. This configuration leads to achieving high gain with keeping a very low profile configuration. Boundary element method with radiation load which takes into account the effect of radiation loss is employed to analyze this complicated configuration. The radiation load, which is very important when boundary element method is applied to antenna analyses, can be obtained from radiation admittance using recurring technique, so that the accuracy of the antenna characteristic calculations can be improved. This antenna was designed and tested in the L-band and good characteristics, axial ratios and radiation patterns, have been verified.

It is highly desirable to develop an efficient and flexible dynamic channel assignment algorithm in order to realize an integrated traffic TDMA mobile radio communication network. In this paper, an integrated traffic TDMA system is studied in which transmission of voice and data are assumed to occupy one and n time slots in each TDMA frame, respectively. In general, there are two types of channel (time slot) assignment algorithms: the partitioning algorithm and the sharing algorithm. However, they are not well-suited to the multimedia traffic consisting of various information sources that occupy different number of slots per frame. In this paper, assuming that voice is much more sensitive to transmission delay than data, an algorithm based on the sharing algorithm with flexible tima slot management scheme is proposed. Our method tries to vary the number of data slots adaptively so as to improve the quality of servive of voice calls and the system capacity. Computer simulations show the good performance of the proposed algorithm when compared to conventional channel assignment algorithms.

The key concept of Physical Optics (PO), originally developed for a perfectly electric conductor (PEC), consists in that the high frequency fields on the scatterer surface are approximated by those which would exist on the infinite flat surface tangent to the scatterer. The scattered fields at arbitrary observation points are then calculated by integrating these fields on the scatterer. This general concept can be extended to arbitrary impedance surfaces. The asymptotic evaluation of this surface integration in terms of diffraction coefficients gives us the fields in analytical forms. In this paper, uniform PO diffraction coefficients for the impedance surfaces are presented and their high accuracy is verified numerically. These coefficients are providing us with the tool for the mechanism extraction of various high frequency methods such as aperture field integration method and Kirchhoff's method.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

This paper explores the potential of multiwave interconnectionsoptical interconnections that employ wavelength components as multiplexable information carriersfor constructing next-generation multiprocessor systems using MCM technology. A hypercube-based multiprocessor network called the multiwave hypercube (MWHC) is proposed, where multiwave interconnections provide highly-flexible dynamic communication channels among processing elements. A performance analysis shows that the use of multiwavelength optics makes possible the reduction of network complexity on an MCM substrate, while supporting low-latency message routing.

This paper presents a new offset-quadrature-phase-shift-keying (OQPSK) coherent demodulation scheme for wireless asynchronous transfer mode (WATM) systems that premise the Ricean fading communication channels (e.g., typically with derectional antennas). The presented demodulator is basically advanced from a simultaneous carrier and bit-timing recovery (SCBR) scheme by newly employing a phase compensated filter and a reverse-modulation scheme for OQPSK. This advancement aims to enhance the carrier phase tracking performance against the phase fluctuation due to the fading and/or the phase rotation caused by the carrier frequency error of the oscillator. Design consideration and performance evaluation of the demodulator are extensively carried out under Ricean fading channels typical of the WATM systems as well as additive white Gaussian noise (AWGN) channels. The evaluation ressults show that the advanced SCBR (ASCBR) scheme achieves a bit-error-rate/cell-error-rate (BER/CER) performance close to ideal coherent detection with a considerably short preamble, e.g., 8 symbols. Specifically, compared with differential detection (evaluated for QPSK with the hard-wired clock), the new coherent demodulator achieves a significant required Eb/No improvement, which becomes larger as the fading condition degrades. This paper concludes that the ASCBR scheme is a strong candidate for the Ricean-fading-premise WATM systems.

A novel learning algorithm for a neural network LSI which has low resolution synapse weights is proposed. Following a brief discussion of the synapse weight adaptation mechanism in the gradient descent scheme, we propose a way of achieving relaxation from the influence of discretized weight. Restriction of the number of synapses to be updated in one learning iteration is effective to relax the influence. Simulation results support the effectiveness of this learning algorithm. Low resolution synapses will be practical to realize large-scale neural network LSIs.

Dynamic Channel Assignment (DCA), which improves the efficiency of channel use in cellular mobile communication systems, requires finding an available channel for a new call after the call origination. This causes the delay which is defined as the time elapsing between call origination and completion of the channel search. For system planning, it is important to evaluate the delay characteristic of DCA because the delay corresponds to the waiting time of a call and influences service quality. It is, however, difficult to theoretically analyze the delay characteristics except its worst case behavior. The time delay of DCA has not been theoretically analyzed. The objective of this paper is analyzing the distribution and the mean value of the delay theoretically. The theoretical techniques in this paper are based on the techniques for analyzing the blocking rate performance of DCA.

We propose a new bit timing recovery (BTR) scheme, what we call Step Sampled BTR (SSBTR), that can lower the sampling clock frequency and shorten the clock phase convergence time, for burst signals in high bit rate wireless access systems. The SSBTR scheme has the following characteristics. A sine wave resulting from the BTR code passing through a Nyquist Transmission System is always used, the sampling clock has a lower frequency than the system clock, and the clock phase of Intermediate Frequency (IF) signal input can be estimated from as few as 3 sampled data. The SSBTR scheme corrects the clock phase only once in a burst signal. Therefore, in some wireless access systems, some kind of operation must be performed after the SSBTR, in order to deal with long burst signals, instability of the system clock, and so on. In other wireless access systems that do not have these problems, clock phase can be fixed by the SSBTR scheme alone. The preformance of the SSBTR scheme with respect to additive white Gaussian noise (AWGN) was examined by computer simulation. In addition, when SSBTR is implemented in hardware, there are imperfections in the circuitry that lead to phase estimation error and thus deterioration, so we studied the effects of several such imperfections by computer simulation. The results of these simulations clarify the performance of the SSBTR scheme.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

An alternative approach to increasing the functional capability of an integrated circuit chip other than the conventional scaling approach is presented and discussed. We will show the functional enhancement at a very elementary device level is essential in implementing intelligent functions at a system level. The concept of a four-terminal device is reviewed as a guiding principle in considering the device functionality enhancement. As an example of a four-terminal device, the neuron MOS transistor is presented. Applications of neuron MOS transistors to several new architecture circuits are demonstrated and the possibility of implementing intelligent functions directly on integrated circuit hardware is discussed.

This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuitsthat is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions, e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

Adaptive maximum likelihood (ML) detection implemented by the Viterbi algorithm (VA) is proposed for the reception of MPSK signals in frequency nonselective fast Rayleigh fading. M-state VA, each state in the VA trellis represents a signal constellation point, is used. Diversity reception is incorporated into the structure of Viterbi decoding. The pilot symbol (unmodulated carrier) is periodically inserted to terminate the trellis so that the phase ambiguity of the detected data sequence is avoided. Applying the per-survivor processing principle (PSPP), adaptive ML detection performs adaptive channel estimation using a simple linear predictor at all trellis states in parallel. The predictor coefficient is stochastically adapted without requiring a priori knowledge of fading channel statistics, based on a recursive least-squares (RLS) adaptation algorithm, to match changes in the statistical properties of the channel (i.e., AWGN of fast/slow fading) using both data and pilot symbols. Simulations of 4PSK signal transmission demonstrate that the proposed adaptive ML detection scheme can track fast fading, thus significantly reducing the irreducible bit error rate (BER) due to Doppler spread in the fading channel. It is also shown that adaptive ML detection provides BER performance close to ideal coherent detection (CD) in AWGN channels.

The segmentation of images into regions that have some common properties is a fundamental problem in low level computer vision. In this paper, the region growing method to segmentation is studied. In the study, a coarse to fine processing strategy is adopted to identify the homogeneity of the subregion of an image. The pixels in the image are checked by a nested triple-layer neighborhood system based hypothesis test. The pixels can then be classified into single pixels or grain pixels with different size and coarseness. Instead of using the global threshold to the region growing, local thresholds are determined adaptively for each pixel in the image. The strength of the proposed method lies in the fact that the thresholds are computed automatically. Experiments for synthetic and natural images show the efficiency of our method.