Many different edge detectors have been proposed. Most of them output the edge intensity and the edge orientation as edge features. In this paper we state necessity of a measure which can discriminate a clear edge with small edge height from a noisy edge with large edge height. To find such a measure as an edge feature, we analyze variances within a window around the edge and propose an edge-feature extractor based on this analysis. Then it is noticed that the traditional edge intensity can be considered as two elements: edge height and edge reliability. In multiple edge cases, the condition is clarified for calculating accurate edge locations by analyzing the edge-height function. From this analysis we suggest a method for determining edge points by thresholding edge height. Our detector is compared to Canny's detector both in synthetic models and in a real image and it is demonstrated that our method produces better results in edge locations than Canny's. We also show that our method can detect edges with low edge height and high edge reliability.

In the proposed architecture, switching system hardware resources are allocated at the equipment level rather than at the component level of LSI chips. Equipment using these resources can thus be shared between independent systems. The efficiency of system development is improved by using structural elements called functional blocks (FBs). The hardware in each FB consists of a shared part (amicroprocessor, its peripheral circuitry, and memory) and a dedicated part that implements the specific functions of the FB. Firmware loaded into the microprocessor consists of a shared part and a dedicated part that corresponds to the hardware parts. Each FB also has its own built-in autonomous testing function to test the reliability of that FB and has its own identification function. By combining these FBs, this approach can flexibly cope with various switching system configurations for plain old telephone service (POTS), integrated services digital network (ISDN), and broad-band ISDN (B-ISDN). Tests using several types of FBs showed that the shared hardware and firmware parts of an FB can be shared between blocks. An architecture based on FBs results in a platform that can handle the hardware for various systems, making it easy to construct new switching systems.

This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

In this paper, we extend the circuit partitioning algorithm which we have proposed for multi-FPGA systems and present a new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it. The core of the presented algorithm is recursive bipartitioning of a circuit. The bipartitioning procedure consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm computes the lower bounds of delays for paths with path delay constraints and detects the critical paths based on the difference between the lower and upper bound dynamically in every bipartitioning procedure. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary inputs and outputs on each critical path to one chip so that the critical path does not cross between chips. Finally in 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional alogorithms.

A wireless tag system has been designed and developed for maintaining and managing outdoor communication facilities. This system employs an infrared (IR) beam and an electromagnetic wave with a radio frequency (RF), and is constructed using IR-RF tags, an IR commander, and an RF receiver. The IR command radiation with strong directivity enables a maintenance operator to recognize a target facility, and the RF response without directivity enables a management system to obtain data from within a large circular area. Solar and secondary batteries are also adopted as the power module in the tag to allow easy maintenance at long intervals. IR signal communication is possible up to a distance of 9 m, and RF signal communication is possible within a circle with a radius of 9 m.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.

A connection admission control (CAC) that guarantees a negotiated cell-loss ratio for all cell-streams passing through the usage parameter control (UPC) in ATM networks is proposed. In particular, the cases in which a jumping-window, sliding-window, or continuous-leaky-bucket scheme are used for peak-cell-rate policing are discussued, and the upper bound for cell-loss ratio of the cell-streams passing through each type of UPC is derived. The CACs based on the derived cell-loss-ratio upper bounds ensure the quality of service in all cases by combining the relevant UPCs. There are three possible combinations of CAC and UPC, depending on the UPC mechanism used. The impact of the choice of CAC and UPC combination on bandwidth utilization is discussed using several numerical examples.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

A leaky-bucket-with-gate algorithm is proposed to control connection-setup congestion in telecommunication networks providing multimedia services, in place of the call-gapping algorithm used in telephone networks. Multimedia services may use more than one connection simultaneously, while standard telephone services use only one connection at a time. A set of connections used to construct a multimedia service is called a correlated connection group, and the setup requests of such a group form correlated request group. A correlated request group is assumed to be accepted into the network only when all the connection-setup requests for the group are accepted. In this paper, the proposed leaky-bucket-with-gate algorithm, a pure leaky-bucket algorithm, and a call-gapping algorithm are evaluated by simulating traffic with a mix of correlated and uncorrelated connection-setup requests, which models setup requests for video conferencing and telephone services. The simulation results show that the proposed algorithm accepts correlated request groups more efficiently than the pure leaky-bucket and call-gapping algorithms under the simulated traffic conditions, except when the interarrival time in a correlated request group is longer than the acceptance interval. We also present queueing analysis for determining the control parameters in the proposed algorithm. Implementation of this algorithm will facilitate the handling of both setup request traffic for correlated connection groups and for uncorrelated connections in multimedia networks.

We developed a 1200 dots-per-inch light emitting diode array (1200 dpi LED array) chip using a GaAs0.8 P0.2 epitaxial substrate for the first time. One LED array chip consists of 256 LEDs. In general, LED arrays are fabricated by vapor-phase zinc diffusion. From the viewpoint that shallow junctions should be formed to fabricate a very high-density LED array, solid-phase diffusion seems to be more suitable. We fabricated the LED array using selectively-masked solid-phase zinc diffusion, and the diffusion depth was controlled at 1 µm. The diffusion depth was uniform under the diffusion window. The ratio of the length of lateral diffusion to the diffusion depth was about 1.7. These features imply that Zn diffusion was well controlled. In the Zn diffusion, the carrier concentration in the Zn diffusion region was high enough and the sheet resistance of the diffusion region with a diffusion depth of 1 µm was low enough to obtain a sufficient level of emitted light power. The results of performance tests showed that the characteristics of the LED array chip are satisfactory for application in optical printer print heads, because of the array's highly-resolved near-field pattern characteristic, ample emitted light power, low emitted-light-power deviation, and long life.

An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

For bonded SOI wafers with active silicon layers thinner than 1 µm, controlling thickness uniformity of active layers has been developed recently. A Plasma Assisted Chemical Etching (PACE) technology is one of methods to realize 0.1 µm bonded SOI. When this technology was proposed for the first time, it was believed that 0.1 µm thick bonded SOI wafers were easily produced independent of initial SOI layer thickness prior to the PACE process. It was true to create 0.1 µm SOI thickness in average. However, the uniformity appeared to be dependent on initial SOI material as well as the PACE machine capability itself. The SOI thickness uniformity pattern after PACE looked like surface morphology of polished silicon wafers. After the experiment to apply various polishing methods to each polishing process in the bonded SOI process, it was verified that the final SOI thickness uniformity after the PACE process was dependent on the waviness of wafer surfaces created in polishing.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

Petri net is a graphical and mathematical tool for modelling, analysis, verification, and evaluation of discrete event systems. Liveness is one of the most important problems of Petri net analysis. This is concerned with a capability for firing of transitions and can be interpreted as a problem to decide whether the system under consideration is always able to reach a stationary behavior, or to decide whether the system is free from any redundant elements. An asymmetric choice (AC) net is a superclass of useful subclasses such as EFCs, FCs, SMs, and MGs, where SMs admit no synchronization, MGs admit no conflicts, FCs as well as EFCs admit no confusion, and ACs allow asymmetric confusion but disallow symmetric confusion. It is known that an AC net N is live iff it is place-live, but this is not the "initial-marking-based" condition and place-liveness is in general hard to test. For the initial-marking-based liveness for AC nets, it is only known that an AC net N is live if (but not only if) every deadlock in N contains a marked structural trap.

This paper presents an efficient optimal block terminal assignment algorithm based on the integer programming for a data path synthesis. The problem is to assign buses to commutable terminals on functional units such that the number of buses is minimum, when the scheduling and allocation of operations and registers have been done. Three methods are used in the algorithm to decrease the amount of computation.