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19821-19840hit(22683hit)

  • An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults

    Tadayoshi HORITA  Itsuo TAKANAMI  

     
    PAPER-Fault Tolerance

      Vol:
    E80-D No:9
      Page(s):
    879-885

    The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

  • Automatic Adjustment of Delay Time and Feedback Gain in Delayed Feedback Control of Chaos

    Hiroyuki NAKAJIMA  Hideo ITO  Yoshisuke UEDA  

     
    PAPER

      Vol:
    E80-A No:9
      Page(s):
    1554-1559

    Methods of automatically adjusting delay time and feedback gain in controlling chaos by delayed feedback control are proposed. These methods are based on a gradient-descent procedure minimizing the squared error between the current state and the delayed state. The method of adjusting delay time and that of adjusting feedback gain are applied to controlling chaos in numerical calculations of Rossler Equation and Duffing equation, respectively. Both methods are confirmed to be successful.

  • TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing

    Vijay K. JAIN  Tadasse GHIRMAI  Susumu HORIGUCHI  

     
    PAPER-Interconnection Networks

      Vol:
    E80-D No:9
      Page(s):
    837-846

    Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.

  • Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer

    Tadayuki SAKAKIBARA  Katsuyoshi KITAI  Tadaaki ISOBE  Shigeko YAZAWA  Teruo TANAKA  Yoshiko TAMAKI  Yasuhiro INAGAMI  

     
    PAPER-Computer Architecture

      Vol:
    E80-D No:9
      Page(s):
    925-932

    We propose an instruction-based variable priority scheme (IBVPS) which achieves high sustained memory throughput on a TCMP type vector supercomputer. Generally, there are two approaches to arbitrating interprocessor memory access conflict: request level priority control and fixed priority control. Each approach, however, affects performance in its own way: In the case of request level priority control, mutual obstruction causes a performance degradation, and in the case of fixed priority control, memory bank monopoly causes a performance degradation. Mutual obstruction refers to the interference among access requests coming from different instructions; memory bank monopoly refers to the un-interrupted accessing of the same memory bank by a series of higher priority instructions. The strategy of the instruction-based variable priority scheme consists in: (a) generally changing the priority assignment of all load/store pipelines at the end of any instruction running in the system, and (b) changing the priority assignment of all load/store pipelines more than once in the middle of an access instruction with a stride greater than 1 or an indirect access instruction which may monopolize some memory banks for an extended period of time. This strategy reduces mutual obstruction because the priority assignment is reshuffled for the entire group of load/store pipelines at a time. it also reduces memory bank monopoly because the opportunity for memory access is made equal among different instructions by changing the priority assignment at the end of an instruction. Moreover, it prevents the memory bank monopoly by a memory access instruction with a stride greater than 1 or an indirect access instruction, by changing the priority assignment more frequently. Consequently, high sustained memory throughput is achieved on TCMP type vector supercomputers.

  • On Information Dumping Phenomenon in Free Recall Effects of Priority Instructions on Free Recall of Pictures and Words

    Atsuo MURATA  

     
    LETTER-Human Communications and Ergonomics

      Vol:
    E80-A No:9
      Page(s):
    1729-1731

    The present study investigated the human ability to selectively process pictures and words in free recall. We explored whether successful bias towards a subset of priority items occurs at the expense of the remaining items-i.e., whether successful priority item bias necessitates the dumping of information related to non-priority items. It has been shown that an increase in the percentage of correct recalls to items given priority in the pre-test instructions induces a decrease in the percentage of correct recalls for non-priority items. Even in a free recall experimental paradigm, the information dumping phenomenon was observed. However, there were no effects of stimulus presentation time and stimulus modality (picture vs. word) on the percentage of correct recalls detected.

  • Waiting-Time Analysis of the Demand-Priority Access Method

    Winston Khoon-Guan SEAH  Yutaka TAKAHASHI  Toshiharu HASEGAWA  

     
    PAPER-Modeling and Simulation

      Vol:
    E80-A No:9
      Page(s):
    1684-1697

    In this paper, we derive the mean message waiting times in a local area network that uses the Demand-Priority Access Method. We model the system as a two-priority M/G/1 queue with switchover time between service periods. This switchover time accounts for the polling and port selection performed by the repeater after each message transmission. The service discipline is non-preemptive and the length of the switchover time is dependent upon the priority class of the preceding message served as well as that of the message to be served next. The dependency in the switchover times is motivated by the polling and port selection operation of the protocol and it makes the analysis much more involved. In order to avoid the complexities of an exact analysis, we make some independence assumptions and thus obtain an approximate solution. Laplace-Stieltjes transforms of the stationary probability distribution functions for the waiting time of high- and normal-priority messages are derived, and subsequently, the expressions for the mean message waiting times. Numerical results computed using these expressions are verified using simulations which model the actual protocol. These numerical results which are shown to be accurate can be easily computed with widely available mathematical software.

  • A Massive Digital Neural Network for Total Coloring Problems

    Nobuo FUNABIKI  Junji KITAMICHI  Seishi NISHIKAWA  

     
    LETTER

      Vol:
    E80-A No:9
      Page(s):
    1625-1629

    A neural network of massively interconnected digital neurons is presented for the total coloring problem in this paper. Given a graph G (V, E), the goal of this NP-complete problem is to find a color assignment on the vertices in V and the edges in E with the minimum number of colors such that no adjacent or incident pair of elements in V and E receives the same color. A graph coloring is a basic combinatorial optimization problem for a variety of practical applications. The neural network consists of (N+M) L neurons for the N-vertex-M-edge-L-color problem. Using digital neurons of binary outputs and range-limited non-negative integer inputs with a set of integer parameters, our digital neural network is greatly suitable for the implementation on digital circuits. The performance is evaluated through simulations in random graphs with the lower bounds on the number of colors. With a help of heuristic methods, the digital neural network of up to 530, 656 neurons always finds a solution in the NP-complete problem within a constant number of iteration steps on the synchronous parallel computation.

  • Environmental Temperature Effect on Magnetization Stability in Particulate Recording Media

    Toshiyuki SUZUKI  Tomohiro MITSUGI  

     
    PAPER

      Vol:
    E80-C No:9
      Page(s):
    1168-1173

    This paper reports the thermal stability of particulate media, which include Co-Fe oxide, CrO2, and thick and thin MP tapes. By measuring the time decay of magnetization at room temperature, fluctuation fields were obtained as a function of reverse applied field. It was clarified that the fluctuation field has a constant and minimum value when the reverse applied field is equal to coercivity. Minimum fluctuation fields for the four particulate tapes were measured at several environmental temperatures ranging from -75 to +100. It was also clarified that the fluctuation field normalized by remanence coercivity increases as the environmental temperature increases for all tapes, indicating that it is a good measure of thermal stability. Activation volumes were also deduced as a function of temperature.

  • Emergent Synchronization in Multi-Elevator System and Dispatching Control

    Takashi HIKIHARA  Shinichi UESHIMA  

     
    PAPER

      Vol:
    E80-A No:9
      Page(s):
    1548-1533

    In this paper, we discuss an emergent behavior of a multi-elevator system. The system includes multiple elevators in an office building and the Poisson arrival of passengers as its input. Elevators move up and down to serve calls and carry passengers according to given working rules. The system is a representative discrete event dynamic system, and is a nonlinear complex system. When people leave a building at the closing time, the down-peak traffic of passengers occurs. We show numerically that (1) this causes a jamming effect, which reduces the transportation efficiency, (2) there exists a threshold in the arrival rate of passengers, at which the traffic rate starts decreasing, and (3) this jamming effect is due to the synchronization of elevators. Then we propose a dispatching control that prevents elevators from synchronizing. This control is applied to each elevator as an anxiliary working rule. We can remove the jamming effect and recover the transportation efficiency by the control.

  • A Current-Mode Sampled-Data Chaos Circuit with Nonlinear Mapping Function Learning

    Kei EGUCHI  Takahiro INOUE  Kyoko TSUKANO  

     
    PAPER

      Vol:
    E80-A No:9
      Page(s):
    1572-1577

    A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.

  • Destructive Fuzzy Modeling Using Neural Gas Network

    Kazuya KISHIDA  Hiromi MIYAJIMA  Michiharu MAEDA  

     
    PAPER

      Vol:
    E80-A No:9
      Page(s):
    1578-1584

    In order to construct fuzzy systems automatically, there are many studies on combining fuzzy inference with neural networks. In these studies, fuzzy models using self-organization and vector quantization have been proposed. It is well known that these models construct fuzzy inference rules effectively representing distribution of input data, and not affected by increment of input dimensions. In this paper, we propose a destructive fuzzy modeling using neural gas network and demonstrate the validity of a proposed method by performing some numerical examples.

  • A Learning Rule of the Oscillatory Neural Networks for In-Phase Oscillation

    Hiroaki KUROKAWA  Chun Ying HO  Shinsaku MORI  

     
    PAPER

      Vol:
    E80-A No:9
      Page(s):
    1585-1594

    This peper proposes a simplified model of the well-known two-neuron neural oscillator. By eliminating one of the two positive feedback synapses in the neural oscillator, learning for the in-phase control of the oscillator is shown to be achievable via a very simple learning rule. The learning rule is devised in such a way that only the plasticity of two synaptic weights are required. We demonstrate some examples of the synchronization learning to validate the efficiency of the learning rule, and finally by illustrating the dynamics of the synchronization learning and by using computer simulation, we show the convergence behavior and the stability of the learning rule for the two-neuron simple neural oscillator.

  • A Computation of Bifurcation Parameter Values for Limit Cycles

    Tetsushi UETA  Masafumi TSUEIKE  Hiroshi KAWAKAMI  Tetsuya YOSHINAGA  Yuuji KATSUTA  

     
    LETTER-Numerical Analysis and Optimization

      Vol:
    E80-A No:9
      Page(s):
    1725-1728

    This letter describes a new computational method to obtain the bifurcation parameter value of a limit cycle in nonlinear autonomous systems. The method can calculate a parameter value at which local bifurcations; tangent, period-doubling and Neimark-Sacker bifurcations are occurred by using properties of the characteristic equation for a fixed point of the Poincare mapping. Conventionally a period of the limit cycle is not used explicitly since the Poincare mapping needs only whether the orbit reaches a cross-section or not. In our method, the period is treated as an independent variable for Newton's method, so an accurate location of the fixed point, its period and the bifurcation parameter value can be calculated simultaneously. Although the number of variables increases, the Jacobian matrix becomes simple and the recurrence procedure converges rapidly compared with conventional methods.

  • Morphological Multiresolution Pattern Spectrum

    Akira ASANO  Shunsuke YOKOZEKI  

     
    PAPER-Digital Signal Processing

      Vol:
    E80-A No:9
      Page(s):
    1662-1666

    The pattern spectrum has been proposed to represent morphological size distribution of an image. However, the conventional pattern spectrum cannot extract approximate shape information from image objects spotted by noisy pixels since this is based only on opening. In this paper, a novel definition of the pattern spectrum, morphological multiresolution pattern spectrum (MPS), involving both opening and closing is proposed. MPS is capable of distinguishing details from approximate information of the image.

  • Efficient Timing Verification of Latch-Synchronized Systems

    Sang-Yeol HAN  Young Hwan KIM  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E80-A No:9
      Page(s):
    1676-1683

    This paper presents an event-driven approach to the timing verification of latch-synchronized systems. The proposed method performs critical path extraction and timing error detection at the same time, and extracts the critical path only if necessary. By doing so, the complexity of analysis is reduced and efficiency is greatly improved over the conventional approaches which detect timing errors after extracting the complete critical paths of the system. Experimental results show that, compared to the existing methods, it provides a more than 12-fold improvement in speed on the average for ISCAS benchmark circuits, and the relative efficiency of analysis improves as the circuit size grows.

  • A High-Speed ATM Switch Based on Scalable Distributed Arbitration

    Eiji OKI  Naoaki YAMANAKA  

     
    LETTER-Switching and Communication Processing

      Vol:
    E80-B No:9
      Page(s):
    1372-1376

    This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed -Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture,and will be suitable for future high-speed multimedia ATM networks.

  • Neural Network Based Photometric Stereo with a Nearby Rotational Moving Light Source

    Yuji IWAHORI  Robert J. WOODHAM  Masahiro OZAKI  Hidekazu TANAKA  Naohiro ISHII  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E80-D No:9
      Page(s):
    948-957

    An implementation of photometric stereo is described in which all directions of illumination are close to and rotationally symmetric about the viewing direction. THis has practical value but gives rise to a problem that is numerically ill-conditioned. Ill-conditioning is overcome in two ways. First, many more than the theoretical minimum number of images are acquired. Second, principal components analysis (PCA) is used as a linear preprocessing technique to determine a reduced dimensionality subspace to use as input. The approach is empirical. The ability of a radial basis function (RBF) neural network to do non-parametric functional approximation is exploited. One network maps image irradiance to surface normal. A second network maps surface normal to image irradiance. The two networks are trained using samples from a calibration sphere. Comparison between the actual input and the inversely predicted input is used as a confidence estimate. Results on real data are demonstrated.

  • Combining Local Representative Networks to Improve Learning in Complex Nonlinear Learning Systems

    Goutam CHAKRABORTY  Masayuki SAWADA  Shoichi NOGUCHI  

     
    LETTER

      Vol:
    E80-A No:9
      Page(s):
    1630-1633

    In fully connected Multilayer perceptron (MLP), all the hidden units are activated by samples from the whole input space. For complex problems, due to interference and cross coupling of hidden units' activations, the network needs many hidden units to represent the problem and the error surface becomes highly non-linear. Searching for the minimum is then complex and computationally expensive, and simple gradient descent algorithms usually fail. We propose a network, where the input space is partitioned into local sub-regions. Subsequently, a number of smaller networks are simultaneously trained by overlapping subsets of the input samples. Remarkable improvement of training efficiency as well as generalization performance of this combined network are observed through various simulations.

  • A Digital Neural Network for Multilayer Channel Routing with Crosstalk Minimization

    Nobuo FUNABIKI  Junji KITAMICHI  Seishi NISHIKAWA  

     
    PAPER-Neural Networks

      Vol:
    E80-A No:9
      Page(s):
    1704-1713

    A digital neural network approach is presented for the multilayer channel routing problem with the objective of crosstalk minimization in this paper. As VLSI fabrication technology advances, the reduction of crosstalk between interconnection wires on a chip has gained important consideration in VLSI design, because of the closer interwire spacing and the circuit operation at higher frequencies. Our neural network is composed of N M L digital neurons with one-bit output and seven-bit input for the N-net-M-track-2L-layer problem using a set of integer parameters, which is greatly suitable for the implementaion on digital technology. The digital neural network directly seeks a routing solution of satisfying the routing constraint and the crosstalk constraint simultaneously. The heuristic methods are effectively introduced to improve the convergence property. The performance is evaluated through solving 10 benchmark problems including Deutsch difficult example in 2-10 layers. Among the existing neural networks, the digital neural network first achieves the lower bound solution in terms of the number of tracks in any instance. Through extensive simulation runs, it provides the best maximum crosstalks of nets for valid routing solutions of the benchmark problems in multilayer channels.

  • An Improved Technique to Measure Nonlinear Phase Shift and Amplitude Distortion

    Naoki HONDA  Takashi KOMAKINE  Kazuhiro OUCHI  

     
    PAPER

      Vol:
    E80-C No:9
      Page(s):
    1194-1202

    A modified frequency domain method for analyzing nonlinear waveform distortion in a magnetic recording process is presented. The measurement technique combines a 5th harmonic measurement technique, which uses a specific 30-bit pattern including dibits, and a precompensation technique for the dibits. The 5th harmonic voltage ratio given by the former technique includes the amount of NLTS (Nonlinear transition shift) and PE (Partial erasure) in dibits. The latter precompensation technique is employed to evaluate the PE as the minimum in the 5th harmonic voltage ratio. The true NLTS can be estimated from the amount of distortion and the evaluated PE. The high accuracy of the technique was confirmed by an examination using a pulse pattern generator with varied phase and amplitude. Finally, the effects of medium properties such as coercivity and squareness on the nonlinear distortions have been investigated by applying the technique to particulate flexible media. The NLTS increased with squareness from 3.5% to 7% while PE was less than 6% for any squareness at a recording density of 76 kFRPI. When coercivity became large, NLTS and PE decreased. The direction of NLTS for Ba-ferrite media agreed with that for a perpendicular Co-Cr thin-film medium.

19821-19840hit(22683hit)