In this paper, we analyze the inverse scattering problem by a new deterministic method called "Source and Radiation Field Solution," which has the merit that both the source and the radiation field can be treated at the same time, the effect of which has already shown in ordinary scattering problems.

This paper studies the application of a media synchronization mechanism to the interleaved transmission of video and audio specified by the H.223 Annex in PHS. The media synchronization problem due to network delay jitters in the interleaved transmission has not been discussed in either the Annex or any related standards. The slide control scheme, which has been proposed by the authors, is applied to live media. We also propose a QOS control scheme to control both quality of the media synchronization and that of the transmission delay. Through simulation we confirm the effectiveness of the slide control scheme and the QOS control scheme in the interleaved transmission.

This paper proposes a novel signal transmission scheme for helicopter satellite communications. The proposed scheme is based on time diversity, and combined with a novel algorithm to suppress an influence of carrier phase slip. In the proposed scheme, carrier phase slip is detected in cross correlation processing of the received signal, and is effectively suppressed. The proposed scheme thus makes it possible to employ coherent phase shift keying modulation to achieve bit error rate performance superior to that of differential phase shift keying modulation even in the low carrier-to-noise power ratio environment.

The software requirements specification process consists of three steps; requirements capture and analysis, requirements definition and specification, and requirements validation. At the beginning of the second step which this paper focuses on, there have been several types of massive documents generated in the first step. Since the developers and the clients/users of the new software system may not have common knowledge in the field which the system deals with, it is difficult for the developers to produce correct requirements specification by using these documents. There has been few research work to solve this problem. The authors have developed a support tool to produce correct requirements specification by arranging and restructuring those documents into clearly understandable forms. In the second step, the developers must specify the functions and their constraints of the new system from those documents. Analyzing the developers' real activities for designing the support tool, the authors propose a model of this step as the following four activities. To specify the functions of the new system, the developers must collect the sentences which may suggest the functions scattering those documents. To define the details of each function, the developers must gather the paragraphs including the descriptions of the functions. To verify the correctness of each function, the developers must survey all related documents. To perform above activities successfully, the developers must manage various versions of those documents correctly. According to these four types of activities, the authors propose the effective ways to support the developers by arranging those documents. This paper shows algorithms based on this model by using the structures of the documents and keywords which may suggest the functions or constraints. To examine the feasibility of their proposal, the authors implemented a prototype tool. Their tool extracts complete information scattering those documents. The effectiveness of their proposal is demonstrated by their experiments.

A zerotree image-coding scheme is introduced that effectively exploits the inter-scale self-similarities found in the octave decomposition by a wavelet transform. A zerotree is useful for efficiently coding wavelet coefficients; its efficiency was proved by Shapiro's EZW. In the EZW coder, wavelet coefficients are symbolized, then entropy-coded for further compression. In this paper, we analyze the symbols produced by the EZW coder and discuss the entropy for a symbol. We modify the procedure used for symbol-stream generation to produce lower entropy. First, we modify the fixed relation between a parent and children used in the EZW coder to raise the probability that a significant parent has significant children. The modified relation is flexibly modified again based on the observation that a significant coefficient is more likely to have significant coefficients in its neighborhood. The three relations are compared in terms of the number of symbols they produce.

Network traffic contains many symptoms of various network faults. Symptoms of faults aggregate and are manifested in the aggregate traffic characteristics generally observed by a traffic monitor. It is very difficult for a manager or an NMS (Network Management Station) to isolate the symptoms manifested in the aggregate traffic characteristics. Especially, transit networks, like a backbone network, deal with many types of traffic. So, symptom isolation must be efficient. In this paper, we propose a powerful algorithm for symptom isolation. This algorithm is based on the popular SNMP-based RMON technology. Using dynamically constructed aggregate, fresh symptoms can be isolated efficiently. We apply the algorithm to two operational transit networks which connects some LANs and WANs, and evaluate it using trace data collected from these networks. The results show a significant improvement in the fault management capability and accuracy. Furthermore, the characteristics of fault symptoms and the various factors for effective system configuration are discussed.

We have developed a Field-Programmable Multi-Chip Module (FPMCM) whose component is the telecommunication-oriented FPGAs, called PROTEUS. The module consists of 3 3 PROTEUS FPGAs and its size is 114 mm square. Each PROTEUS chip is mounted on the MCM substrate using Tape Automated Bonding (TAB) technology so as to minimize the size of the MCM and the production cost. The interconnection topology among the FPGAs is a simple mesh. However, the connection can be changed logically, because PROTEUS itself has a special inter-I/O bypass resource in it. Using this mechanism, the interchip connection delay can be reduced without sacrificing the flexibility, compared to the previous FPMCM implementation using some other interconnection switches which often have a large propagation delay. The interchip connection delay is 200 ps. We have also developed a rapid prototyping system comprising several MCMs, and implemented telecommunication circuits in it.

A Pragmatic Trellis Coded MPSK on a Rayleigh fading channel is analyzed. This scheme allows bandwidth expansion ratio to be varied aiming at an optimization between complexity of the system design and improvement of coding gain. In order to vary the bandwidth expansion ratio, a punctured convolutional code is used. The performance of the proposed TC-2mPSK on a Rayleigh fading channel is theoretically analyzed. In the test examples, the BER performances of TC-QPSK and TC-8PSK are evaluated by theoretical analyses and computer simulations at the encoder parameters of K3 and r3/4. The results show that the proposed scheme can attain better performance not only over the uncoded scheme but over the conventional Pragmatic TCM.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.

Conventional approach for frequency estimation usually assume a single tone without data modulation. In many applications such an assumption, realized by using either a separate pilot beacon or synchronization preamble is not feasible. This paper deals with frequency estimation of phase-modulated carriers in the absence of timing information and known data pattern. We introduce new frequency estimators that are based on the generalized maximum likelihood principle. The communication channels under consideration include both additive white Gaussian noise (AWGN) channels and correlated Rician fading channels. For the latter class, we distinguish between the case when the fading (amplitude) process is tracked and that when it is not tracked.

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

The mapping from a global routing to a feasible detailed routing in a number of 2D array routing structures has been shown to be an NP-complete problem. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA routing structures called Greedy Routing Architectures (GRAs) have been proposed. On GRAs, optimally routing each switch box, in a specified order, leads to an optimal chip routing. Because routing each switch box takes polynomial time, the mapping problem on GRAs can be solved in polynomial time. In particular, an H-tree GRA with W2+2W switches per switch box (SpSB) and a 2D array GRA with 4W2+2W SpSB have been proposed. In this paper, we improve on these results by introducing an H-tree GRA with W2/2+2W SpSB and a 2D array GRA with 3.5W2+2W SpSB. These new GRAs have the same desirable mapping properties of the previously described GRAs, but use fewer switches.

The importance of technology retargeting for hard IPs is getting increased. However, recent advances in process technologies make layout reuse too complicated to be done by conventional compactors. As an efficient approach, this paper proposes a flexible layout abstraction model and a new layout synthesis algorithm. The synthesis algorithm provides a concurrent procedure of detailed wiring, compaction, and transistor layout generation by using a scan line to get better layout results than conventional compactors. We have applied this method to the technology retargeting of actual cell layouts and have achieved quite good results comparable to hand-crafted designs.

Analysis of frequency-dependent lossy transmission lines is very important for designing the high-speed VLSI, MCM and PCB. The frequency-dependent parameters are always obtained as tabulated data. In this paper, a new curve fitting technique of the tabulated data for the moment matching technique in the interconnect analysis is presented. This method based on Chebyshev interpolation enhances the efficiency of the moment matching technique.

Consider a random digraph G=(V,A), where |V|=n and an arc (u,v) is present in A with probability p(n) independent of the existence of the other arcs. We discuss the expected number of vertices reachable from a vertex, the expected size of the transitive closure of G and their related topics based on the properties of reachability, where the reachability from a vertex s to t is defined as the probability that s is reachable to t. Let γn,p(n) denote the reachability s to t (s) in the above random digraph G. (In case of s=t, it requires another definition. ) We first present a method of computing the exact value of γn,p(n) for given n and p(n). Since the computation of γn,p(n) by this method requires O(n3) time, we then derive simple upper and lower bounds γn,p(n)U and γn,p(n)L on γn,p(n), respectively, and in addition, we give an upper bound n,p(n) on γn,p(n)U, which is easier to analyze but is still rather accurate. Then, we discuss the asymptotic behavior of n,p(n) and show that, if p(n)=α/(n-1), limnn,p(n) converges to one of the solutions of the equation 1-x-e-α x=0. Furthermore, as for (n) and (n), which are upper bounds on the expected number of reachable vertices and the expected size of the transitive closure of G, resp. , it turns out that limn(n) =α/(1-α) if p(n)=α/(n-1) for 0<α<1; otherwise either 0 or , and limn(n)=α if p(n)=α/(n-1)2 for α0; otherwise either 0 or .

This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.

In order to enhance the energy transfer efficiency in a Cherenkov laser, we propose to use a tapered waveguide with a dielectric thickness properly varied stepwise in the longitudinal direction. With the aid of particle simulation, we investigate the nonlinear characteristics of the Cherenkov laser with the tapered waveguide, demonstrating the effectiveness of our proposal for efficiency enhancement.

Network survivability against various unexpected failures is one of indispensable technologies for the B-ISDN infrastructure. Self-healing algorithm is the technique to automatically restore the failed VP's (virtual paths) in the backbone ATM network. Since the B-ISDN transports various kinds of traffic with various levels of priority (Grade of Service: GoS), the effective self-healing algorithm should orderly restore the failed VP's based on the priority of their traversing traffic. This paper proposes the priority based restoring self-healing algorithm, which realizes the priority based restoring function by the two-timer mechanisms and a simple capacity reserving protocol. The simulation results show that the proposed algorithm can schedule the restoration process so that the failed VP's with higher priority are restored before the others with lower priority. In addition, the significant improvement in restoration speed for the highest priority traffic class has been achieved.

One of unique features of CDMA slotted ALOHA (CDMA S-ALOHA) is that user must synchronize his transmission to given slot. Thus orthogonal sequence as spreading sequence would achieve ideal throughput if each of packets accomplish perfect synchronization. In the presence of any ambiguity in synchronizations, however, quasi-synchronous (QS) sequences suit well with CDMA S-ALOHA system. In this paper, we introduce new QS-sequences obtained from the orthogonal Gold sequences and discuss their performance when applying to CDMA S-ALOHA systems. As a result, withstanding to access timing error, good performance is ensured with this sequence under the environment of AWGN, MAI (multiple access interference) and frequency non-selective fading, that is, micro or pico cellular systems and indoor wireless LANs.