This paper presents the subjective speech quality evaluation in terms of the Mean Opinion Score (MOS) and the relationship between BER and subjective speech quality in a GSM-based radio system. The results show that in certain environments (hilly terrain and rural areas), a SNR (or C/I) higher than 12 dB is required for acceptable speech quality. For an acceptable speech quality, a BER(c1) better than 10-2 is needed in a GSM-based system.

YBa2Cu3Ox films were grown on MgO(100) substrates by liquid phase epitaxy. Their structural and electrical properties were examined. From TEM plan-view images, it is found that the film consists of large grains whose misorientation angles are less than 1. Although the DC critical current density values decrease with increasing the film thickness, the critical current density value of 9. 3105 A/cm2 at 77 K is obtained for a 7 µm-thick film. A microstrip resonator at 10. 8 GHz with a YBCO ground plane shows Q0 values of 14200 at 77 K and 23300 at 40 K, which correspond to surface resistance values of 650 and 400 µΩ, respectively. By using a microstrip line resonator with a Ti/Au ground plane, the critical field of the film at 77 K and 10. 8 GHz is estimated to be 30 Oe. The third-order intercept of the resonator with the Ti/Au ground plane is the input power of +43 dBm and the output power of +30 dBm at 77 K.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

This paper is concerned with the validation of simple turning points of two-point boundary value problems of nonlinear ordinary differential equations. Usually it is hard to validate approximate solutions of turning points numerically because of it's singularity. In this paper, it is pointed out that applying the infinite dimensional Krawcyzk-based interval validation method to enlarged system, the existence of simple turning points can be verified. Taking an example, the result of validation is also presented.

Related with accuracy, computational complexity and so on, quality of computing for the so-called homotopy method has been discussed recently. In this paper, we shall propose an estimation method with interval analysis of region in which unique solution path of the homotopy equation is guaranteed to exist, when it is applied to a certain class of uniquely solvable nonlinear equations. By the estimation, we can estimate the region a posteriori, and estimate a priori an upper bound of the region.

Modeling error is the major concerning issue in the trajectory estimation. This paper formulates the dynamic model of a reentry vehicle in reentry phase for identification with an unmodeled acceleration input covering possible model errors. Moreover, this work presents a novel on-line estimation approach, adaptive filter, to identify the trajectory of a reentry vehicle from a single radar measured data. This proposed approach combines the extended Kalman filter and the recursive least-squares estimator of input with the hypothetical testing scheme. The recursive least-squares estimator is provided not only to extract the magnitude of the unmodeled input but to offer a testing criterion to detect the onset and presence of the input. Numerical simulation demonstrates the superior capabilities in accuracy and robustness of the proposed method. In real flight analysis, the adaptive filter also performs an excellent estimation and prediction performances. The recommended trajectory estimation method can support defense and tactical operations for anti-tactical ballistic missile warfare.

This paper describes an efficient simulation algorithm for the spatiotemporal pattern analysis of the continuous-time neural networks with the multivalued logic (multivalued continuous-time neural networks). The multivalued transfer function of neuron is approximated to the stepwise constant function which is constructed by the sum of the step functions with the different thresholds. By this approximation, the dynamics of the network can be formulated as a stepwise constant linear differential equation at each timestep and the optimal timestep for the numerical integration can be obtained analytically. Finally, it is shown that the proposed method is much faster than a variety of conventional simulators.

This paper gives two kinds of functions for which Uesaka's Conjecture, stating that the globally optimum (not a local minimum) of a quadratic function F(x)=-(1/2)xtAx in the n-dimensional hypercube may be obtained by solving a differential equation, holds true, where n denotes the dimension of the vector x. Uesaka stated in his paper that he proved the conjecture only for n=2. This corresponds to a very special case of this paper. The results of this paper suggest that the conjecture really holds for a wide class of quadratic functions and therefore support the conjecture partially.

The naturalness of normal sustained vowels is considered to be attributable to the fluctuations observed in the steady part where speech signal is seemingly almost periodic. There always exist two kinds of involuntary fluctuations in the steady part of sustained vowels, even if the sustained vowels are phonated as steadily as possible. One is pitch period fluctuation and the other is waveform fluctuation. In this study, frequency analyses on these fluctuations were conducted in order to investigate their general characteristics. The results of the analyses suggested that the frequency characteristics of the fluctuations were possible to be approximated as 1/fβ-like, which is regarded as the specific feature of random fractal. Therefore, a procedure based on random fractal generation methods was proposed in order to produce these fluctuations for the improvement of the voice quality of synthesized sustained vowels. A series of psychoacoustic experiments was also conducted to evaluate the proposed technique. Experimental results indicated that the proposed technique was effective for synthesized sustained vowels to be perceived as human-like. Unlike the sustained vowels which were synthesized without pitch period fluctuation nor waveform fluctuation, the synthesized sustained vowels which contained the fluctuations were not perceived as buzzer-like, which is the major problem of the voice quality of synthesized sustained vowels. However, it was also found that both of the fluctuations were not always the acoustic cues for the naturalness of normal sustained vowels. The synthesized sustained vowels which contained the fluctuations whose frequency characteristics were the same as that of white noise were perceived as noise-like, which is not at all the voice quality of normal sustained vowels. The results of psychoacoustic experiments indicated that the frequency characteristics of the fluctuations, which are possible to be modeled as 1/fβ-like, were the significant factors for the naturalness of normal sustained vowels.

We here consider an extension of the validity of classical criteria ensuring the robustness of the statistical features of discrete time dynamical systems with respect to implementation inaccuracies and noise. The result is achieved by proving that, whenever a discrete time dynamical system is robust, all the discrete time dynamical systems topologically conjugate with it are also robust. In particular, this result offer an explanation for the stochastic robustness of the logistic map, which is confirmed by the reported experimental measurements.

In this paper, we show that two-dimensional billiards with point interactions inside exhibit a chaotic nature in the microscopic world, although their classical counterpart is non-chaotic. After deriving the transition matrix of the system by using the self-adjoint extension theory of functional analysis, we deduce the general condition for the appearance of chaos. The prediction is confirmed by numerically examining the statistical properties of energy spectrum of rectangular billiards with multiple point interactions inside. The dependence of the level statistics on the strength as well as the number of the scatterers is displayed.

Synchronization between two fully stretching piecewise affine Markov maps in the usual master-slave configuration has been proven to be possible in some interesting 2-dimensional and 3-dimensional cases. Aim of this contribution is to make a further step in the study of this phenomenon by showing that, if the two systems synchronize, the probability of having a certain synchronization time is bounded from above by an exponentially vanishing distribution. This result gives some formal ground to the numerical evidence shown in [2].

The second generation of mobile communications is growing rapidly to the third generation due to various communication techniques and the increasing number of users. PCS, the communication method of the third generation, should be able to provide users with various services, independently of the current location. To PCS, the mobility management of users is essential. The mobility management method which has been used has a structural drawback: as the number of users increase, HLR becomes the bottleneck. Everyone is expected to have one terminal in the third generation mobile communications age. Therefore, an enhanced mobility management scheme to reduce the bottleneck of the HLR, should be used in the third generation mobile communications. In this paper, we propose a new mobility management method where the trace of terminals is left in the VLRs, so that a call can be connected by querying only to the VLRs rather than to the HLR when the terminal-terminated-call occurs. The proposed method distributes messages to VLRs and effectively reduce mobility management cost. To estimate overall mobility management cost, we simulated the new method of PCS network. The simulation model is based on the Jackson's network, and makes it possible to estimate mobility management cost of PCS networks. IS-41 and proposed scheme are compared based on the computer simulation. Considering the delay times both in HLR and VLR, and considering both location registration cost and call delivery cost, the proposed modeling method shows the improvement.

In this paper we propose a total quality evaluation method in an ATM network-type remote conference system, and describe the results of evaluations of a proving system. The quality of a remote conference system depends on such various elements as video images, voice signals, and cost; but a total quality index may be regarded as the cost of a remote conference system compared with that of a conventional face-to-face conference. Here, however, the decline in communication quality arising from the remote locations of participants must be included in the evaluation. Moreover, the relative weightings of voice signals, video images of participants, and shared data will vary depending on the type of conference, and these factors must also be taken into account in evaluations. An actual conference systems were constructed for evaluation, and based on a MOS (Mean Opinion Score) of the quality elements, the total system quality was evaluated with reference to the proposed concepts. These results are also described in this paper.

In this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined with computation in the processor pipeline. The pipeline is enhanced with hardware mechanisms to support fine-grain parallel execution. The data paths of the RICA-1 super-scalar processor are commonly used for communication as well as instruction execution to minimize its implementation cost. A 128-PE system has been built on January 1998, and it is currently used for hardware debugging, software development and performance evaluation.

In the design of an embedded system, an architecture of core processor strongly affects the performance and cost of the total system. This paper discusses a scalable processor architecture, called soft-core processor, which can be tuned for a target system. System designers can optimize several design parameters such as the datapath width and instruction set, and generate customized processors for their application. Design of Bung-DLX as a prototype of soft-core processor is presented in this paper. An experiment of system design using our processor has shown that the optimized processor chip area halves when the critical path delay is reduced to one third of the original one.

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs can be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16. 4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. In order to reconsider the DRAM data retention characteristics, this paper formulates and evaluates the performance degradation due to conflicts between normal DRAM accesses and refresh operations. Next, this paper proposes a new DRAM refresh architecture which intends to reduce unnecessary refreshes. This architecture exploits multiple refresh periods. Each row is refreshed with the most appropriate period of them. Reducing the number of refreshes improves the accessibility to DRAM. It is shown that the method reduces the number of refreshes and the degree of the performance degradation of the logic portion.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.