In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

The hybrid electrical/optical multi-chip integration technique for optical modules for optical network system has been developed. Employing the technique, a 44 broadcast-and-select type optical matrix switch module has been realized. The module consists of four sets of silica waveguide 1 : 4 splitters/4 : 1 combiners, four 4-channel arrays of polarization insensitive semiconductor optical amplifiers with spot-size converters as optical gates, printed wiring chips for electrical wiring and single mode fibers for optical signal interface on planar waveguide platform fabricated by atmospheric pressure chemical vapor deposition. All the gates and the wiring chips were mounted precisely onto the platform at once in flip-chip manner by self-align technique using AuSn solder bumps. Coupling loss between the waveguide and the SOA gate was estimated to be 4.5 dB. Averaged fiber-to-fiber signal gain, on-off ratio and polarization dependent loss for each of the signal paths was 7 dB 2 dB, more than 40 dB and 0.5 dB, respectively. High speed 10 Gb/s photonic cell switching as short as 2 nsec has been successfully achieved.

Given two terms and their rewriting rules, an unreachability problem proves the non-existence of a reduction sequence from one term to another. This paper formalizes a method for solving unreachability problems by abstraction; i. e. , reducing an original concrete unreachability problem to a simpler abstract unreachability problem to prove the unreachability of the original concrete problem if the abstract unreachability is proved. The class of rewriting systems discussed in this paper is called β rewriting systems. The class of β rewriting systems includes very important systems such as semi-Thue systems and Petri Nets. Abstract rewriting systems are also a subclass of β rewriting systems. A β rewriting system is defined on axiomatically formulated base structures, called β structures, which are used to formalize the concepts of "contexts" and "replacement," which are common to many rewritten objects. Each domain underlying semi-Thue systems, Petri Nets, and other rewriting systems are formalized by a β structure. A concept of homomorphisms from a β structure (a concrete domain) to a β structure (an abstract domain) is introduced. A homomorphism theorem (Theorem1)is established for β rewriting systems, which states that concrete reachability implies abstract reachability. An unreachability theorem (Corollary1) is also proved for β rewriting systems. It is the contraposition of the homomorphism theorem, i. e. , it says that abstract unreachability implies concrete unreachability. The unreachability theorem is used to solve two unreachability problems: a coffee bean puzzle and a checker board puzzle.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

Wavelength division multiplex (WDM) photonic networks are expected as the key for the global communication infrastructure. Recent increase of communication demands require large-scale highly-dense WDM systems, which results in severe requirements for optical cross-connect systems, such as cross-talk specification. In this paper, we propose a new optical path cross-connect system (OPXC) using matrix-WDM scheme, which makes it possible to reduce cross-talk requirements of WDM filters and to construct OPXC in modular structures. The matrix-WDM scheme is a concept of two-layered optical paths, which provides wavelength group managements in the fiber dispersion equalization and EDFA gain equalization.

One of the most important problems in machine learning is to predict a binary value by observing a sequence of outcomes, up to the present time step, generated from some unknown source. Vovk and Cesa-Bianchi et al. independently proposed an on-line prediction model where prediction algorithms are assumed to be given a collection of prediction strategies called experts and hence be allowed to use the predictions they make. In this model, no assumption is made about the way the sequence of bits to be predicted is generated, and the performance of the algorithm is measured by the difference between the number of mistakes it makes on the bit sequence and the number of mistakes made by the best expert on the same sequence. In this paper we extend the model by introducing a notion of investment. That is, both the prediction algorithm and the experts are required to make bets on their predictions at each time step, and the performance of the algorithm is now measured with respect to the total money lost, rather than the number of mistakes. We analyze our algorithms in the particular situation where all the experts share the same amount of bets at each time step. In this shared bet model, we give a prediction algorithm that is in some sense optimal but impractical, and we also give an efficient prediction algorithm that turns out to be nearly optimal.

A novel testing-pad placement method has been developed to greatly improve E-beam observability for multi-level wiring LSIs. In the method, testing pads connecting a lower-metal-layer wire with a top-metal-layer electrode are positioned in the design layout, making removal of the insulator unnecessary. The method features i) pad placement in unoccupied areas in mask patterns to avoid increases in chip size, ii) minimized pad size through the use of stacked vias so that the pads can be placed on as many wire nodes as possible, iii) placement as far as possible from the nearby wires to avoid local field effects, and iv) allocation of one testing pad to one circuit node to minimize the number of testing pads. These measures give us a practical pad-placement method, that has little influence on LSI design. It was shown that the proposed method yielded a dramatic improvement of observability from 13-33% to 88-99% in actual layouts of 0.25-µm ASICs with 20k, 120k, and 390k gates. It was also found that local field effects from nearby wires are negligible for almost all the testing pads. This approach will enable the use of E-beam testing on LSIs made with 0.25-µm technology and the even more sophisticated process technologies to come.

We suggest an MAC scheme which combines a hash function and an block cipher in order. We strengthen this scheme to prevent the problem of leaking the intermediate hash value between the hash function and the block cipher by additional random bits. The requirements to the used hash function are loosely. Security of the proposed scheme is heavily dependent on the underlying block cipher. This scheme is efficient on software implementation for processing long messages and has clear security properties.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with fT of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

Lots of self-tuning control schemes have been proposed for tuning the parameters of control systems. Among them, pole-assignment schemes have been widely used for tuning the parameters of control systems with unknown time delays. They are usually classified into two methods, the implicit and the explicit methods according to how to identify the parameters. The latter has an advantage to design a control scheme by taking account of the stability margin and control performance. However, it involves a considerably computational burden to solve a Diophantine equation. A simple scheme is proposed in this paper, which can construct a multivariable self-tuning pole-assignment control system, while taking account of the stability margin and control performance without solving a Diophantine equation.

This paper proposes a method to transform a CORDIC ARMA lattice filter, which is originally realized for signal analysis, into a signal synthesis lattice filter (CORDIC ARMA lattice synthesis filter). In order to perform such a transformation and then obtain the CORDIC ARMA lattice synthesis filter, we must implement the followings with CORDIC: (1) the structure of the altered lattice filter; and (2) an angle calculation module. However, we cannot achieve such an implementation as an extension of the CORDIC ARMA lattice filter algorithm. Therefore, this paper proposes CORDIC implementation schemes for both the structure and module, and then we realize the CORDIC ARMA lattice synthesis filter. By using CORDIC processors, the elementary sections of the CORDIC ARMA lattice synthesis filter are efficiently implemented without any multipliers. Since the obtained signal synthesis lattice filter consists of dedicated CORDIC processors, it keeps the advantage of the CORDIC ARMA lattice filter, that is a simple structure.

The pseudo-inverse model for the associative memory has an iterative algorithm converging to its weight matrix. The present letter shows that the same algorithm except for the lack of self couplings can be derived by simple consideration of the energy of the network state.

This paper reviews the hyper-media photonic information network (HM-PIN) concept as a candidate of innovative future networks based on photonic technologies. The HM-PIN having a universal network interface integrates a variety of information services: telecommunications, newspapers, magazines, TV broadcasts and the growing collection of information servers. This network fundamentally offers three items: (1) bi-directional real-time channels with 10-Mbit/s-class or higher bit rate, (2) multipoint connections including multicasting/broadcasting, (3) high accessibility to information. These items are derived from the constraints of the conventional telephone networks and the Internet. By applying photonic technologies, the HM-PIN can be implemented as follows: The local network (the service platform) of the HM-PIN can be achieved by using a wavelength-division-multiplexing (WDM) broadcast-and-select (B&S) architecture that offers broadband multipoint connections (one-to-many, many-to-many) based on an inherent full-mesh topology. The WDM B&S local network will be able to support 10,000 to 100,000 channels (each with 10-Mbit/s or more bandwidth) by using optical and electrical multiplexing techniques. The backbone network can be constructed by combining photonic asynchronous transfer mode (ATM) switching systems and WDM transmission systems (including cross-connects). Two deployment scenarios of the HM-PIN (cost-oriented and service-oriented deployment scenarios) are also described for smoothly introducing the HM-PIN even before the cost issue is solved. The HM-PIN based on photonic technologies will be a future network service platform that greatly enhances communication services.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

An optical cell buffer (OCB) for use in photonic ATM switch, is needed in order to resolve contention between optical cells. A 320-Gb/s-throughput switch system with 32 wavelength channels requires a buffer size of 13 and a wavelength bandwidth of 25 nm. We developed an optical cell buffer with a four-nested-taps configuration and fabricated it with electroabsorption gates and gain clamped optical amplifiers. The output level variation, which determines the stability of operating condition, is less than 2.4 dB under typical conditions and the insertion loss variation is suppressed to within 5 dB. This OCB can be used in a 320-Gb/s photonic ATM switch.

This paper describes the implementation and demonstration of local networks for the hyper-media photonic information network (HM-PIN), a candidate for the information service platform offering broadcast and telecommunication services. In addition, the feasibility of the HM-PIN is also demonstrated using prototype local network systems. This local network adopts architecture based on wavelength-division-multiplexing (WDM) and broadcast-and-select (B&S) switching, and supports all HM-PIN services except inter-local-network communication. The major issues of this proposed network are the technologies that support many broadcast channels and reduce channel selection cost. This paper also considers the combination of WDM technology and three alternatives: electrical TDM, subcarrier multiplexing (SCM or electrical FDM), and optical TDM (O-TDM). Three 128 ch (8 wavelengths 16 channels) WDM B&S prototype systems are built to demonstrate the feasibility of the proposed HM-PIN. In WDM/SCM, 30 and 20 Mb/s channels are realized as 16-QAM and 64-QAM, and 155 Mb/s channels are realized by WDM/TDM. Moreover, these three prototypes were connected to form a small HM-PIN and applications such as video distribution and IP datagram cut-through are demonstrated. Furthermore, the delay and throughput of the HM-PIN are evaluated by connecting a local network to a 200-km WDM-ring backbone network. Our discussions and demonstrations confirm the impact and feasibility of the proposed hyper-media photonic information network.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

To enhance the extinction ratio (ER) of NRZ-to-inverted-RZ converter based on cross-gain compression of a semiconductor optical amplifier (SOA), a modified terahertz optical asymmetric demultiplexer (TOAD) is cascaded. ER is improved from 1.6-6.7 dB to 5.4-14.5 dB, depending on the intensity of input optical NRZ signal. The proposed NRZ-to-inverted-RZ converter enhances and regulates ER to a high value (14.5 dB) for very wide optical NRZ signal intensity range.

A 116 arrayed waveguide grating multiplexer operating around 1550 nm has been realized using newly synthesized fluorinated poly(arylene ethers). The channel spacing is 0.8 nm (100 GHz). The insertion loss of the multiplexer is 17-20 dB and the cross talk is less than -15 dB. The propagation loss of a rib waveguide is less than 0.5 dB/cm at 1550 nm.