In an iterative decoding algorithm, such as Chase Type-II decoding algorithm and its improvements, candidate codewords for a received vector are generated for test based on a bounded-distance decoder and a set of test error patterns. It is desirable to remove useless test error patterns in these decoding algorithms. This paper presents a sufficient condition for ruling out some useless test error patterns. If this condition holds for a test error patterns e, then e can not produce a candidate codeword with a correlation metric larger than those of the candidate codewords generated already and hence e is useless. This significantly reduces the decoding operations in Chase type-II decoding algorithm or decoding iterations in its improvements.

The symbol basis side information generated by Viterbi's ratio threshold test technique is proposed to improve the performance of the asynchronous slow-frequency-hopped multiple access system with BFSK signaling in the frequency non-selective fading channel. By properly setting the ratio threshold to produce erasure decisions for the received symbols, the system performances are optimized. The relationship among the hit symbols in a hop duration is exploited by this symbol basis side information to greatly reduce the packet error probability. This packet error rate improvement can be as large as two order of magnitude, compared with perfect hop basis side information systems.

In [1] a generalized concatenated code was used to construct the t-fold unidirectional b-bit-byte error-correcting/d(dt)-fold unidirectional b-bit-byte error-detecting (t-UbEC/d(t)-UbED) codes. The concatenated code is to choose an inner code satisfying some disjoint sets and each set is a binary b-tuples unordered code. However, [1] gave five methods including trial and error to construct the optimal inner codes. Here, we present a systematic method for constructing the inner codes. It is shown that we can improve the coding efficiency for t-UbEC/d(t)-UbED) codes in some cases by using our inner codes.

The Asynchronous Transfer Mode (ATM) and the switches and other network elements based on this principle have matured significantly over the past few years. Extensive field trials have been successfully performed all over the world and an increasing number of operators is starting to offer regular services based on ATM infrastructures. The general trend towards deregulation and liberalization resulting in an increasing competition among network providers world wide creates a strong push towards flexible, high-performance, cost effective infrastructures for data, voice, video and multimedia communication. ATM has the potential to provide the universal platform for this future B-ISDN because it combines the features of classical telecommunication networks with features required to cope with the increasing demand for computer based communication. Therefore, ATM allows a consolidation of all existing, dedicated networks for the various services onto a common network platform and at the same time provides a solid and future proof basis for new services and applications. To make this ATM-based multiservice platform a favorable option for large wide area networks, the reliability known from the classical voice networks has to be provided in addition to a virtually unlimited scaleability of the switching systems and of the network as a whole. Whereas the support of permanent connections, i. e. the application of simple VP-crossconnects, was adequate for the first trial networks, on-demand connections controlled by powerful signaling systems have to be provided in the future broadband networks. Moreover, the rather simple resource allocation and traffic management functions used in the first ATM networks have to be extended to be able to guarantee an application specific quality of service while optimizing the use of the available network resources and, thus, to be able to fully exploit the inherent capabilities of the ATM principle. Another crucial point for the success of the ATM multiservice platform is the efficient interworking with existing networks, especially with the narrowband ISDN, the Frame Relay or SMDS based public data networks and with TCP/IP based Internets. This paper describes a new generation ATM switch which fully exploits the capabilities of todays technology to implement the full functionality necessary to cope with these requirements. It introduces the basic architectural concepts, the functionality and some implementation aspects of this large, highly reliable ATM switch which has been specifically designed for application in the core of a future B-ISDN. Special emphasis is put on the concept and realization of the switch fabric which can be scaled from a few Gbit/s into the Tbit/s range.

Predicting the performance of high speed wide area ATM networks (WANs) is a difficult task. Evaluating the performance of these systems by means of mathematical models is not yet feasible. As a result, the creation of simulation models is usually the only means of predicting and evaluating the performance of such systems. In this paper, we use measurements to validate simulation models of TCP/IP over high speed ATM wide area networks. Validation of simulations with measurements is not common; however, it is needed so that simulation models can be used with confidence to accurately characterize the performance of ATM WANs. In addition, the appropriate level of complexity of the simulation models needs to be determined. The results show that under appropriate conditions simulation models can accurately predict the performance of complex high speed ATM wide area networks. This work also shows that the user perceived performance is dependent on host processing demands.

Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.

The ATM switching system accommodating the public switched telephone network (PSTN) and narrowband ISDN (N-ISDN) subscribers should ensure the continued support of existing services and applications and guarantee the same quality of voice services for the telephone users. The voice message connection control discussed in this paper is one of the various technical issues for voice services in the interworking function unit, IWF between asynchronous transfer mode (ATM) node and existing synchronous transfer mode (STM) node [2]. We describe the technical points for the implementation of the voice message connection control with the consideration of the development time and cost. And then we discuss several technical problems such as mapping pulse code modulation PCM coded voice data into an ATM cell, different switching operation, keeping performance of the ATM-PSTN interworking system and then present benefits of the voice message connection control processing from the hardware/software point of views.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

We study buffer access policies which provide different loss priorities between two types of services, namely, real-time and nonreal-time services in ATM networks. Real-time services, such as video and voice, require the cell transmission with bounded delay. For these services, their available buffer sizes are limited by the delay bounds. We compare the performance of several buffering policies with bounded delay constraints of real-time services. Numerical results indicate that a simple buffering policy, called limited partial buffer sharing (LPBS) proposed in this paper, has a good performance for efficient use of ATM networks.

The paper is focused on the architectural and technological solutions that will allow the transition from small to huge capacity ATM Switching Systems. This path starts from the industrial nodes available today and will arrive at the photonic switching architecture. The progressive introduction of photonics has already started with the use of optical interconnections in ATM nodes of hundreds of Gbit/s. A balanced use of microelectronics and photonics is the correct answer to the Terabit/s switching system challenge. After presenting a modular ATM Switching System, some technological solutions like Multichip Modules and Optical Interconnections are presented in order to explain how node capacity can be expanded. Some results of the research activity on photonic Switching are finally shown in order to exploit the great attitude of this technique to obtain very high throughput nodes.

In this paper, we propose a high performance highly modular ATM switch architecture known as Bodhi which is suitable for small, large, and very large size ATM switch implementations. Its basic configuration consists of two stages: an input stage and an output stage. The input stage consists of input group modules (IGMs) and output stage output group modules (OGMs). Each IGM-OGM pair is connected by multiple paths which carry cells from IGMs to OGMs. Excess cells at the IGMs are recycled to minimize the cell loss probability. Another module called recirculation module is used to couple several IGMs together to create additional routes for recirculating cells which gives this architecture robustness against nonuniform and directed traffic. Multicasting has been implemented by integrating copying and broadcasting techniques, and using some novel techniques to minimize the switch complexity. A shared buffer architecture is employed for OGMs such that it implements multiple priorities dynamically in a weighted manner, requires no speedup, and, can function in standalone mode as small switches. The performance of Bodhi has been evaluated by computer simulation to select design parameters for a 1k 1k (k=1024) switch fabric. It allows growability from 2. 4 gigabit to 150 gigabit switch, and, expandability to 100+ Terabit switch with the complexity increasing approximately linearly with size. Based on the study presented in this paper, it is seen that the Bodhi architecture offers a high degree of modularity, weighted dynamic priority control, robustness against nonuniform traffic conditions, low complexity, low latency, and, supports multicasting efficiently and without any limitation. Bodhi, therefore, has high potential for application in high speed broadband networks.

This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.

In this paper, we discuss configurations of photonic ATM (Asynchronous Transfer Mode) switches and their advantages in terms of the number of optical switching devices to be implemented on the system, the number of wavelengths, throughput, broadcast function etc. In particular, we focus on photonic ATM switch architectures which can be built in the near future; that is, with presently available optical and electrical devices. For example, we assume the optical devices such as optical gate switches with 40 dB on/off ratio. In this context, we evaluate 17 types of photonic ATM switches; they are 6 types of input buffer type switches, 6 types of output buffer type switches, 4 types of shared buffer switches, and 1 proposed type. From our evaluation, for cell switching, wavelength division switching technologies are desirable compared with space division switching technologies in the sense that the former enables us to build a photonic ATM switch with the less number of optical gate switches. Furthermore, we propose a switch architecture equipped with optical delay line buffers on outputs and electric buffers on inputs. We show that our switch architecture is superior in the number of required optical gate switch elements under the given conditions.

We propose a mechanically tunable passively mode-locked semiconductor laser with a high repetition rate using a simple configuration with a moving mirror located very close to a laser facet. This scheme is demonstrated for the first time by a novel micromechanical laser consisting of an InGaAsP/InP multisegment laser with a monolithic moving micro-mirror driven by an electrostatic comb structure. The main advantage of this laser is the capability of generating high-quality mode-locked pulses stabilized by a phase-locked loop (PLL) with low residual phase noise in a wide repetition-rate tuning range. This paper describes the basic concept and tuning performances utilizing the micromechanical passively mode-locked laser in 22-GHz fundamental mode-locking and in its second-harmonic mode-locking.

Typical concepts concerning memorizing capability of multilayer neural networks are statistical capacity and Vapnik-Chervonenkis (VC) dimension. These are differently defined each other according to intended applications. Although for the VC dimension several tighter upper bounds have been proposed, even if limited to networks with linear threshold elements, in literature, upper bounds on the statistical capacity are available only by the order of magnitude. We argue first that the proposed or ordinary formulation of the upper bound on the statistical capacity depends strongly on, and thus, it is possibly expressed by the number of the first hidden layer units. Then, we describe a more elaborated upper bound of the memorizing capacity of multilayer neural networks with linear threshold elements, which improves former results. Finally, a discussion of gaining good generalization is presented.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

This paper presents a new architecture of a high-speed ATM switch. The switch, called FSM (Factorial Style Memory) switch, uses Dual-Port memories to construct a factorial style memory for eliminating the bus contention problem. In order to fit the various applications, based on the proposed switch architecture, several kinds of models are also proposed to construct the larger size of switches. With the same required throughput and cell loss probability, the performance analysis of the switch shows that the number of buffers and average cell delay can be significantly reduced in the proposed switch while comparing to the ATM switches with central shared memory. For satisfying applications that require larger switches, three types of expansion methods which contain size expansion, memory expansion, and size-memory combined expansion are discussed.

In this paper, two universal building blocks for complex filter using CCIIs, CFCCIIs, grounded resistors and grounded capacitors are presented. These can be used to realize various complex bandpass filters with arbitrary order. The paper shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of the conventional one employing op-amps, and that the sensitivities for all components are relatively small. Experimental results are used for verifying the validity of the proposed circuits.

We propose new key exchange and authentication protocols, which are efficient in protecting a poorly-chosen weak secret from guessing attacks, based on the use of a one-time pad and a strong one-way hash function. Cryptographic protocols assume that a strong secret should be shared between communication participants for authentication, in the light of an ever-present threat of guessing attacks. Cryptographically long secret would be better for security only if ordinary users could remember it. But most users choose an easy-to-remember password as a secret and such a weak secret can be guessed easily. In our previous work, we made much of introducing a basic concept and its application. In this paper, we describe our idea in more detail and propose more protocols which correspond to variants of our basic protocol using well-defined notations. Formal verification and efficiency comparison of the proposed protocols are also presented. By our scheme the password guessing attacks are defeated efficiently, and a session key is exchanged and participants are authenticated securely.