A more judicious choice of trial functions to implement the Improved Circuit Theory (ICT) application to multi-element antennas is achieved. These new trial functions, based on Tai's modified variational implementation for single element antennas, leads to an ICT implementation applicable to much longer co-planar dipole arrays. The accuracy of the generalized impedance formulas is in good agreement with the method of moments. Moreover, all these generalized formulas including the radiation pattern expressions are all in closed-form. This leads to an ICT implementation which still requires much shorter CPU time and lesser computer storage compared to method of moments. Thus, for co-planar dipole arrays, the proposed implementation presents a relatively very efficient method and would therefore be found useful in applications such as CAD/CAE systems.

An adaptive array has been proposed as a canceller for both inter-symbol interference (ISI) and co-channel interference (CCI). However, it has no path-diversity gain since it selects just one signal correlated to the reference signal. In this paper, a novel interference canceller having sufficient path-diversity gain is proposed. The canceller is characterized by the combined configuration of an adaptive array and an equalizer. In the proposed system, a pre-selecting adaptive array is installed first. By employing a specific training sequence and sampling timing at the receiver during the training period, the perfect correlation between the "desired signal" and "short delayed" is achieved. Therefore, the pre-selecting adaptive array can extract the desired and ISI signals simultaneously, and the cascaded adaptive equalizer can provide the path-diversity gain without degradation by interference. The proposed system achieves a simple configuration and robustness against both ISI and CCI with a sufficient path diversity gain. In computer simulations, average BER characteristics of the proposed system were evaluated in a quasi-static Rayleigh fading channel. The simulation results showed that the system can reduce both long-delayed ISI and CCI efficiently, and that the expected path diversity gain is obtained even with strong CCI. They also showed that the degradation is not so serious when the number of antenna elements is less than that of incoming signals.

In this letter, we propose new methods for estimating frequency and phase of a complex sinusoid in complex white Gaussian noise. These new estimators use the cyclostationarity of the sinusoid which is a cyclostationary signal type. Only one component corresponding to a lag of zero of cyclic autocorrelations is used to reduce the computational load. The performances of our proposed estimators are compared to those of Kay estimator, Cramer-Rao bound (CRB) and maxim-likelihood estimator (MLE). Simulation results show that our proposed methods can estimate the frequency and phase correctly even in low signal-to-noise ratio (SNR).

Method schemas were proposed as a formal model of object-oriented languages. A method schema S is called consistent if, for each method invocation during the execution of S, a method definition to be bound to the invoked method name is uniquely determined. However, the consistency testing problem is known to be undecidable in general. This paper presents an algorithm which analyzes the consistency of a given method schema. The algorithm decides the consistency problem in polynomial time for monadic method schemas. We also provide an incremental algorithm for testing consistency after updates of a method schema.

This letter newly proposes the polarity-reversing type photonic receiving scheme based on bipolar correlation for optical CDMA signal in radio highway. The proposed scheme can more improve the limitation of the number of radio base stations connected to radio highway and more reduce the peak laser power at the radio base station than the conventional unipolar type receiving scheme using prime codes.

A training data selection method is proposed for multilayer neural networks (MLNNs). This method selects a small number of the training data, which guarantee both generalization and fast training of the MLNNs applied to pattern classification. The generalization will be satisfied using the data locate close to the boundary of the pattern classes. However, if these data are only used in the training, convergence is slow. This phenomenon is analyzed in this paper. Therefore, in the proposed method, the MLNN is first trained using some number of the data, which are randomly selected (Step 1). The data, for which the output error is relatively large, are selected. Furthermore, they are paired with the nearest data belong to the different class. The newly selected data are further paired with the nearest data. Finally, pairs of the data, which locate close to the boundary, can be found. Using these pairs of the data, the MLNNs are further trained (Step 2). Since, there are some variations to combine Steps 1 and 2, the proposed method can be applied to both off-line and on-line training. The proposed method can reduce the number of the training data, at the same time, can hasten the training. Usefulness is confirmed through computer simulation.

Digital signal processors (DSPs) usually employ indirect addressing using an address register (AR) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. In this paper, AR update scheme is extended such that address can be efficiently modified by 2 in addition to conventional 1 updates. An automatic address allocation method of program variables for this new addressing model is presented. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained triangle graph, which is accessed only by AR 1 and 2 operations, so that the estimated number of overhead codes is minimized. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods.

Vehicular speed response phase locked loop (VSR-PLL) is a novel circuit to remove a steady-state frequency offset which arises in the receiver with directive antenna. In this paper, the circuit is applied to Ricean fading environment. For the application of VSR-PLL to Ricean statistics channel, the Doppler shift information of direct wave must be obtained because the self-oscillation frequency of VCO is controlled by using the information. This paper describes an estimation method for the Doppler shift of the direct wave, and shows the several results of the performance analysis for the estimation method and proposed VSR-PLL with the method. As a result, we found that the proposed VSR-PLL could reduce the irreducible bit-error rate for QPSK system from about 10-2 to 10-3 on several conditions.

In a DC 50 V/5 A circuit, the relationship between the number of breaking arcs and the spatial distribution of the spectral intensity of breaking arcs of long duration near the cathode in palladium contact were examined through substitution of the contact surfaces of three different shapes: flat and spherical (1 mm radius and 2 mm radius). Findings show the distribution of spectral intensity in Pd arcs to be influenced remarkably by the shape of contact surface and the number of breaking arcs. However, the temperature of Pd arcs was affected neither by the shape of contact surface nor by the number of breaking arcs. The metal-vapor quantity present differed for flat and spherical surface contacts; however, it was not affected by the radius of the curved contact surfaces or by the number of breaking arcs. Additionally, the longer the duration of the breaking arc, the more metal-vapor was presented in the beginning of the arc. Furthermore, arc tracks on contact surfaces were observed with microscopes, clarifying that the relationship between the area of the clouded white metal on the cathode and the shape of contact surface is the same as the relationship between the existent area of measured spectra and the shape of the contact surface.

Solder joint reliability was studied for hybrid ICs, in which chip components such as FETs, resistors and capacitors were mounted with Sn-Sb solder on an insulated Al substrate and transfer-molded with epoxy resin. Suitable resin selection for molding was also studied. The structure was estimated to have a lifetime of more than ten thousand cycles in the thermal cycling test under the condition of -55/150, for FETs and passive elements. Equivalent plastic strains generated in the soldering layer for the non-molded structure were 4. 6% for the FETs and 3.5% for the passive elements. But, these strains were approximately 1/3 to 1/2 and 1/10 for the molded structure, respectively. This was the main reason for high reliability of the molded structure. Resins with a wide range of thermal expansion coefficient(8-26 ppm/)could be put to practical use, because of the higher reliability of the molded structure. However, a thermal expansion coefficient of about 15 ppm/ was prefered to decrease stress at the interface between the substrate and the molding resin.

This paper studies a congestion control scheme in integrated variable bit-rate video, audio and data (e. g. , image or text) communications, where each video stream is synchronized with the corresponding audio stream. When the audio and video streams are output, media synchronization control is performed. To avoid congestion, we employ a dynamic video resolution control scheme which dynamically changes the video encoding rate according to the network loads. By simulation, the paper evaluates the performance of the scheme in terms of throughput, loss rate, average delay, and mean square error of synchronization. Numerical results show the effectiveness of the scheme.

This correspondence reports novel computationally efficient algorithms for multiplication of bicomplex numbers, which belong to hypercomplex numbers. The proposed algorithms require less number of real multiplications than existing methods. Furthermore, they give more effective implementation when applied to constant coefficient digital filters.

Widely tunable coherent terahertz (THz)-wave generation was successfully demonstrated based on the laser light scattering from the lowest A1-symmetry polariton mode by using a Q-switched Nd:YAG laser pumping. This method exhibits multiple advantages like wide tunability (frequency: 0. 9-2. 2 THz), coherency and compactness of its system. In this paper, the general performances of this THz-wave generator, as well as the recent development of the system and its application are reported. Measurements of tunability, coherency, power, polarization, radiation angle, and divergence are shown. The cryogenic cooling of the crystal was performed in addition, and a more than one hundred times higher THz-wave output was observed. A spectroscopic application of our wave source is demonstrated by measuring the water vapor absorption.

This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 88 banyan-based subnetwork using 0. 25-µm CMOS/SIMOX technology can attain a 40-Gbit/s switching capability.

While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

This paper evaluates the throughput performance of a switch architecture for broadband networks that is capable of switching variable-length packets. The structure is connectionless, so that no bandwidth reservation takes place before the user packet, or datagram, is transferred. The interconnection network is assumed to be internally non-blocking and provided with input queues. A previous approximated throughput analysis of the proposed system has been carried out under the hypothesis that the length of the offered packets is uniformly distributed. In this work we perform an exact throughput analysis and we show how the actual throughput of the system can be expressed analytically with a simple closed form. Moreover, we consider a more general case of packet length distributed as a truncated exponential. In this way it is possible to account for cases in which short packets are more frequent than long packets or, conversely, long packets are more frequent than short ones. The minimum throughput of the system is obtained when packets are uniformly distributed; a better performance is obtained when short (long) packets are more frequent than long (short) ones.

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

We present a finite-difference time-domain (FD-TD) method with the perfectly matched layers (PMLs) absorbing boundary condition (ABC) based on the multidimensional wave digital filters (MD-WDFs) for discrete-time modelling of Maxwell's equations and show its effectiveness. First we propose modified forms of the Maxwell's equations in the PMLs and its MD-WDFs' representation by using the current-controlled voltage sources. In order to estimate the lower bound of numerical errors which come from the discretization of the Maxwell's equations, we examine the numerical dispersion relation and show the advantage of the FD-TD method based on the MD-WDFs over the Yee algorithm. Simultaneously, we estimate numerical errors in practical problems as a function of grid cell size and show that the MD-WDFs can obtain highly accurate numerical solutions in comparison with the Yee algorithm. Then we analyze several typical dielectric optical waveguide problems such as the tapered waveguide and the grating filter, and confirm that the FD-TD method based on the MD-WDFs can also treat radiation and reflection phenomena, which commonly done using the Yee algorithm.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.

An ultra-broadband optical parametric amplification can be attained by a noncollinear phase-matching. The group-velocity matching of the signal and idler reduces the signal-pulse width to 14-fs in an optical parametric amplifier based on a β-BaB2O4 crystal pumped by a second harmonics of a Ti: sapphire regenerative amplifier. This simple novel method shows the potential light source of a tunable sub-10-fs pulse in a visible region.