An adaptive stability-growth (ASG) learning algorithm is proposed for improving, as much as possible, the stability of a Hopfield-type associative memory. While the ASG algorithm can be used to determine the optimal stability instead of the well-known minimum-overlap (MO) learning algorithm with sufficiently large lower bound for MO value, it converges much more quickly than the MO algorithm in real implementation. Therefore, the proposed ASG algorithm is more suitable than the MO algorithm for real-world design of an optimal Hopfield-type associative memory.

A simple method of compensating the DC drift of LiNbO3 Mach-Zehnder intensity modulators for very high speed optical transmission systems is proposed. This method adds low frequency perturbation to the modulator driving signal, and controls the bias voltage using the detected envelope of the modulator output signal. The control circuit is successfully demonstrated to work with less than a 0. 1-dB power penalty.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

An adaptive infinite impulse response (IIR) filter implemented using an allpass and a minimum phase system has an advantage of its poles converging to the poles of the unknown system when the input is a white signal. However, when the input signal is colored, convergence speed deteriorates considerably, even to the point of lack of convergence for certain colored signals. Furthermore with a colored input signal, there is no guarantee that the poles of the adaptive digital filter (ADF) will converge to the poles of the unknown system. In this paper we propose a method which uses a linear predictor filter to whiten the input signal so as to improve the convergence characteristic. Computer simulation results confirm the increase in convergence speed and the convergence of the poles of the ADF to the poles of the unknown system even when the input is a colored signal.

The channel throughput and packet delay of wireless medium access control (MAC) protocols with Rayleigh fading, shadowing and capture effect are analyzed. We consider CSMA/CA protocols as the wireless MAC protocols, since CSMA/CA protocols are based on the standard for wireless Local Area Networks (LANs) IEEE 802. 11. We analyze the channel throughput and packet delay for three types of CSMA/CA protocols; Basic CSMA/CA, Stop-and-Wait CSMA/CA and 4-Way Handshake CSMA/CA. We calculate the capture probability of an Access Point (AP) in a channel with Rayleigh fading, shadowing, and near-far effects, and we derive the throughput and packet delay for the various protocols. We have found that the performance of CSMA/CA in a radio channel model is 50 percent less than in an error free channel model in low traffic load, while the throughput and packet delay of CSMA/CA in a radio channel model show better performance than in an error free channel model in high traffic load. We also found that the 4-Way Handshake CSMA/CA protocol is superior to the other CSMA/CA protocols in high traffic load.

This paper proposes practical escrow cash schemes with particular emphasis on countermeasures against social crimes such as money laundering and extortion. The proposed cash schemes restrict "unconditional" privacy in order to prevent these social crimes while preserving off-line-ness, divisibility and transferability, properties listed in [25] as criteria for ideal cash schemes.

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

In this paper a public key certification scheme, which protects privacy of user of the public key certificate, is proposed. In the proposed scheme a certification authority issues anonymous public key certificates, with which a certificate user having his/her own secret key can make use of public key cryptography and a certificate verifier can confirm the authenticity of the cryptographic communication of the certificate user. The anonymity of their users is preserved against the verifier. In general, user's activities should not be linked each other from the viewpoint of privacy protection. The use of the same certificate results in the linkage of the cryptographic communications. So, ideally, a certificate should be used only once, and such a certificate is called a one-time certificate. In the proposed scheme one-time certificates are realized with low cost of communication and computation for the certificate user. Multiple certificates can be issued without interaction between CA and the user. The additional computation of the user to obtain a new anonymous public key certificate is one modular exponentiation. In addition, only one secret key is required for multiple certificates. Therefore, the proposed scheme is useful for applications which require anonymity, unlinkability, and efficiency.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

This letter gives a study of additionY=X+K mod 2w which is used in some cryptosystems as RC5. Our results enables us to express the differential and linear probability of addition as a function of addendK. To detect a good differential characteristics or linear approximation of a cryptosystem in which extended key is used as addend, we need to consider how the characteristics or approximations behave depending upon the value of the addend, which are clarified by our results.

In this paper, we present an analytic model to study the reliability of some important disk array organizations that have been proposed by others in the literature. These organizations are based on the combination of two options for the data layout, regular RAID-5 and block designs, and three alternatives for sparing, hot sparing, distributed sparing and parity sparing. Uncorrectable bit errors have big effects on reliability but are ignored in traditional reliability analysis of disk arrays. We consider both disk failures and uncorrectable bit errors in the model. The reliability of disk arrays is measured in terms of MTTDL (Mean Time To Data Loss). A unified formula of MTTDL has been derived for these disk array organizations. The MTTDLs of these disk array organizations are also compared using the analytic model. By numerical experiments, we show that the data losses caused by uncorrectable bit errors may dominate the data losses of disk array systems though only the data losses caused by disk failures are traditionally considered. The consideration of uncorrectable bit errors provides a more realistic look at the reliability of the disk array systems.

We propose a novel opto-electronic memory device using a single quantum dot (QD) and a logic device using coupled QDs (CQD) which performs (N)AND and (N)OR operations simultaneously. In both devices, occupation/unoccupation by a single electron in a QD is viewed as a bit 1/0 and data input/output (I/O) is performed by irradiation/absorption of photons. The (N)AND/(N)OR operations are performed by the relaxation of the electronic system to the Fock ground state which depends on the number of electrons in the CQD. When the device is constructed of semiconductor nanostructures, the main relaxation process is LA-phonon emission from an electron. Theoretical analysis of the device shows that (i) the error probability in the final state converges with the probability with which the system takes excited states at thermal equilibrium, i. e. , depends only on the dissipation energy and becomes smaller as the dissipation energy becomes larger, and (ii) the speed of operation depends on both the dissipation energy and dissipative interactions and becomes slower as the dissipation energy becomes larger if LA-phonon emission is taken into account. If the QDs are InAs cubes with sides of 10 nm and they are separated by the AlSb barrier with a width of 10 nm, the speed of operation and the error probability are estimated to be about 1 ns and about 0. 2 at 77 K, respectively. The basic idea of the device is applicable to two-dimensional (2D) pattern processing if the devices are arranged in a 2D array.

Time spread (TS) pulse position modulation (PPM) signals have been proposed for CDMA applications, where the envelope detection is employed instead of coherent detection for easier synchronization of PPM. In this paper, a new method of deriving symbol error probability (SEP) of TS PPM signals in the presence of interference is introduced. The analysis is based on the moment technique. The maximum entropy criterion for estimating an unknown probability density function (PDF) from its moments is applied to the evaluation of PDF of envelope detector output. Numerical results of SEP are shown for 4, 8 and 16PPM in the practical range of signal-to-noise power ratio (SNR) and signal-to-interference power ratio (SIR) of 5, 10 and 20 dB. SEP by the union bound is also given for comparison. From the results it is noted that when PPM multilevel number is small, the union bound goes near to SEP by the proposed method, but when it increases the difference of the SEP by the bound and proposed method becomes larger. The effect of central frequency offset of TS-filter is evaluated as an illustrative example.

We describe an algorithm for efficiently compositing partial images generated during parallel volume rendering on a distributed memory parallel computer. In this object space partitioning algorithm, each PE is assigned to several subvolumes where each subvolume has a corresponding local frame buffer. After volume rendering is performed independently for each subvolume, the partial images stored in the local frame buffers are combined to generate a complete image. During this compositing process, the communication of partial image data between the PEs is kept minimal by assigning PEs to subvolumes in an interleaved manner. This assignment makes possible a reduction in communication in the axis direction in which there is the most communication. Experimental results indicate that a 9% to 35% reduction in the total rendering time can be attained with no additional data structures and no memory overhead.

The Optimal Packet Length (OPL) in packet-switched communication systems has been studied in the literature from various aspects. In this paper, we consider the trade-off between packet length and data transmission delay in a high-speed communication system. To simplify the analysis of the mean data transmission delay, the model is limited to a point-to-point communication system, in which each node complies with the OSI reference model. In order to study the relationship between the OPL and the number of modules performing each protocol, two model communication systems are discussed. In one each node contains two layered protocol modules, and in the other three. Moreover, for both models, the mean data transmission delay is analyzed for two cases depending on whether or not the DLC layer or the network layer performs retransmissions. After studying the OPL which minimizes the mean data transmission delay in each case, we discuss the relationships between the OPLs and the various protocol parameters.

This paper analyzes a finite buffer M/G/1 queue with two classes of customers who are served by a combination of head-of-the-line priority and push-out schemes. This combination gives each class of customers two different types of priorities with respect to both delay and loss. There are two models considered. The first one is that one class of customers has a higher priority over the other class with respect to both delay and loss; the second one is that one class has a higher priority with respect to loss and the other has high-priority with respect to delay. For both of these models, the joint probability distribution of the number of customers of both classes in the buffer is derived by a supplementary variable method. Using this probability distribution, we can easily calculate the loss probabilities of both classes, the mean waiting time for high-priority customers with respect to loss and the upper bound for mean waiting time for low-priority customers with respect to loss. Numerical examples demonstrate an effect of the combination of different types of priorities.

Recently reported multidimensional geometrically uniform signal constellations (L MPSK and Decomposed-Lattice constellations) are joined in the term of Generalized Permutation Alphabets (GPA). Possibility of a binary isometric labeling of GPA's is completely characterized. An algorithm for constructing generating groups of PSK-type GPA is proposed. We show that this concept, when is extended to the lattice, gives rise to a class of new coset codes which perform out best codes listed in [11].