This paper extends left-incompatible term rewriting systems defined by Toyama et al. It is also shown that the functional strategy is normalizing in the class, where the functional strategy is the reduction strategy that finds index by some rule selection method and top-down and left-to-right lazy pattern matching method.

A rigorous analysis of coupling between two twin-slot antennas using the Finite Difference Time Domain (FDTD) method is reported for the first time. The Phase Cancellation Effect (PGE) is used to reduce the coupling due to the TM0 surface wave mode between the Coplanar Waveguide (CPW) fed cascade-connected twin-slot antennas. To confirm the effectiveness of this approach, coupling between single-slot and twin-slot elements separated by λ0/2 was analysed. The coupling between the two single-slot antennas was S21 = -30.2 dB. For the case of two twin-slot antennas, the coupling was found to be -37.8 dB, 7.6 dB below that of the single-slot antennas. The phase cancellation effect of surface waves is significant in reducing coupling between two twin-slot antennas, in addition to minimising power loss into substrate modes. A memory optimised implementation of the FDTD method with the Berenger Perfectly Matched Layer (PML) Absorbing Boundary Condition (ABC) was used for the numerical analysis.

For traffic control in high speed ATM Networks Usage Parameter Control (UPC) plays an important role. The existing UPC schemes have some limitations. It is difficult to implement policy which involves monitoring vioations while guaranteeing QoS for the compliant connections-particularly with respect to bursty traffic sources. This is due to the difficulty in measuring the Sustained Cell Rate (SCR) and Maximum Burst Size (MBS) parameters simultaneously. To ensure prompt action against policy-violations, speedy detection is an important requirement. But the existing UPC schemes do not have a satisfactory response time. In this paper, we propose a new scheme called Markovian State-Dependent UPC schemes (MSDU) to police SCR and MBS parameter violation simultaneously with a satisfactory response time. The MSDU scheme is performed by using two virtual queues: 1) a Markovian State Dependent Service queue and 2) a Fixed Service queue. The discrete time analysis of the MSDU is carried out for a bursty source which is a Markov-Modulated Bernoulli Process (MMBP). The improved effectiveness of the proposed MSDU is clarified by a numerical comparison with UPC based on standard Leaky Bucket scheme.

This paper proposes high-speed similitude retrieval schemes for a viewpoint-based similarity discrimination system (VB-SDS) and presents analytical and experimental performance evaluations. The VB-SDS, which contains a huge set of semantic definitions of commonly used words and computes semantic similarity between any two words under a certain viewpoint, promises to be a very important module in analogical and case-based reasoning systems that provide solutions under uncertainty. By computing and comparing similarities for all words contained in the system, the most similar word for a given word can be retrieved under a given viewpoint. However, the time this consumes makes the VB-SDS unsuitable for inference systems. The proposed schemes reduce search space based on the upper bound of a similarity calculation function to increase retrieval speed. An analytical evaluation shows the schemes can achieve a thousand-fold speedup and confirmed through experimental results for a VB-SDS containing about 40,000 words.

In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.

The bit error rate (BER) performance against average Eb/No (signal energy per bit-to-noise power spectral density ratio) and the capacity of the pilot symbol-assisted coherent orthogonal filter (PSA-COF) based Rake receiver with fast transmit power control (TPC) are evaluated in DS-CDMA reverse link under multipath Rayleigh fading. Fast TPC, which controls all signals transmitted from users in the same cell or sector such that they are received with equal power at the cell site under fast Rayleigh fading, is essential for the PSA-COF based Rake receiver in the reverse link in order to improve the performance degradation experienced when the received signal level drops due to fading as the transmit power is limited in practical systems. Signal-to interference plus noise power ratio (SINR) based fast transmit power control (TPC) is assumed here. By using the fast TPC in reverse link and applying the PSA-COF based Rake receiver to base station (BS), the transmit power of each mobile station (MS) can be significantly reduced, thus increasing link capacity. It is demonstrated that the capacity of the PSA-COF based Rake receiver is about 1.5 times higher than that of the conventional matched filter (MF) receiver in interference-limited channels.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

Various high-performance SOI CMOS circuits were fabricated using fully-depleted 0.25-µm gate MOSFETs on a low-dose SIMOX substrate. 2.4-Gbps operations were achieved for I/O and speed conversion circuits which are key elements in a multimedia communication LSI. LVTTL-compatible gate array LSI was developed with an ESD protection circuit which is the first one to meer the MIL standard. A 120-kG test LSI was fabricated on the gate array, and the LSI performances using three kind of technologies; 0.25-µm bulk and SIMOX and 0.5-µm bulk; were compared. A 0.25-µm SIMOX LSI was 10% faster with 35% less power dissipation compared with a 0.25-µm bulk LSI. The 0.25-µm SIMOX LSI can operate at a VDD of 1.2 V to attain the same speed as the 0.5-µm bulk LSI operating at 3.3 V, and this results in 1/40 power reduction. For the high-speed communication use, an ATM-switch LSI with 220-kG and a 110-kb memory was fabricated. A high-performance of 2.5-Gbps interface speed and 312-Mbps internal speed were achieved using 0.25-µm CMOS/SIMOX. This ATM-switch LSI has the greatest bandwidth of 40-Gbps ever reported using a one-chip ATM-switch LSI.

We report on 1.9-GHz performance of the Buried-Channel self-aligned WN/W-gate GaAs MESFET (BC-MESFET) for use in digital mobile telephone handsets with low power consumption. The BC-MESFET incorporates undoped i-GaAs epitaxial-grown surface layer on the ion-implanted channel. Both the power and noise performance of the BC-MESFET are superior to the conventional MESFET. The 0.6-µm gate power BC-MESFET exhibits a high power-added efficiency of 57% at 1-dB gain compression, which leads to low power dissipation of the handset. This power performance is attributed to high breakdown voltage which the undoped i-GaAs surface layer has brought about. The BC-MESFET has also shown a minimum noise figure of below 0.4 dB. Taking the IC-oriented fabrication process of the BC-MESFET into consideration, these FET performances demonstrate that the BC-MESFET is suitable for the single-chip MMIC that integrates RF front-end blocks for the 1.9-GHz small-size mobile telephone handset with long battery lifetime.

This paper proposes a direct-sequence spread spectrum (DS/SS) communication system with a new diversity technique designed for indoor multi-path fading channels where path diversity isn't available. In this system, the transmitter sends a same signal from multiple antennas at the same time with intentional time delays, which allows the receiver to distinguish and combine the signals from different antennas. We also consider the combination of this scheme with the conventional receiving antenna diversity for additional diversity gain. Furthermore, it is found that the use of the multiple transmitting antennas decreases the effect of the multiple access interference.

We propose a spread-spectrum power line communication system considering the cyclic features of the noise in the lines. For this purpose, we model the noise as the sum of a time-invariant stationary process and two cyclostationary proceses, i.e., cyclic continuous noise and cyclic impulsive noise. The proposed system employs two different countermeasures to each of these two classes of cyclic noise. For the cyclic continuous noise, it uses multiple-processing-gain spread spectrum technique: the smaller processing gains are assigned for the periods with lower instantaneous noise power and the larger ones for the periods of higher noise power. Considering the cyclic impulsive noise, convolutional coding with interleaving is applied. In order to analyze the performance improvement due to the employment of multiple processing gains, we introduce a simple model of the continuous noise. The overall performance is evaluated by computer simulation with the actual noise wave-form measured in power lines.

An MT connector assembly machine has been designed and developed. The connector assembly time using this machine is about 30% less than with the conventional method. The MT connectors assembled employing this machine have a low connection loss and stable mechanical characteristics.

A wireless communications system with a transmission rate of 10 Mbit/s using Japanese ISM band (2471-2497 MHz) is presented. This system employs a novel spread spectrum multiple access method named "CFO-SS (Carrier Frequency Offset-Spread Spectrum)" method. In the CFO-SS system, a single PN code is commonly assigned to all the multiple carriers, and the frequency offset between the carriers is determined by the information symbol rate, which is small as compared with the spread bandwidth of the signal. Bit error rate performance of the proposed CFO-SS system under multipath environments is investigated by computer simulation, and the performance of the CFO-SS method is confirmed for wireless LAN systems using the 2.4 GHz ISM band.

In general cases of pattern recognition, a pattern to be recognized is first represented by a set of features and the measured values of the features are then classified. Finding features relevant to recognition is thus an important issue in recognizer design. As a fundamental design framework taht systematically enables one to realize such useful features, the Subspace Method (SM) has been extensively used in various recognition tasks. However, this promising methodological framework is still inadequate. The discriminative power of early versions was not very high. The training behavior of a recent discriminative version called the Learning Subspace Method has not been fully clarified due to its empirical definition, though its discriminative power has been improved. To alleviate this insufficiency, we propose in this paper a new discriminative SM algorithm based on the Minimum Classification Error/Generalized Probabilistic Descent method and show that the proposed algorithm achieves an optimal accurate recognition result, i.e., the (at least locally) minimum recognition error situation, in the probabilistic descent sense.

The performance of a constrained (that is, minimal order) Yule-Walker (CYW) single tone frequency estimator is studied. A closed form expression for the asymptotic error variance is derived. It is shown that CYW does not satisfactorily utilize the informaiton in data, and estimators with improved performance are proposed. Simulation results which lend support to the theoretical findings are included.

Recently, progress has been made in the area of electrical modeling of conductors embedded in arbitrary dielectrics using circuit oriented techniques. These models usually occur in conjunction with VLSI type circuits. Many different applications exist today for such models in the EMI, EIP (Electrical Interconnect and Package) analysis as well as for the microwave circuit area. Practical problems involve a multitude of hardware components and they demand a wide spectrum of both time as well as frequency domain solution techniques. In this paper we consider circuit oriented techniques for the solution of these problems. Specifically, we give an outline of the three dimensional Partial Element Equivalent Circuit (PEEC) full wave modeling approach and review the recent progress in this area.

A novel block coding scheme based on complementary sequences which is capable of both error correction and peak to average power ratio reduction has been proposed for M-ary PSK multicarrier systems. Generator matrices for the number of carriers N = 2k where k = 2,3,...are derived. The effectiveness of the scheme has been confirmed by computer simulations.

In this paper we consider all self-orthogonal [n, 1/2(n-1)] codes for n odd and 3 n 19, all self-dual [n, 1/2n] codes for n even and 2 n 24 and some other codes over GF(2) and answer to a question which of them have efficient coordinate ordering. As a result the exact values of their state complexities are determined. Sufficient conditions for codes to have an efficient coordinate ordering are derived also.

The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include a growing system complexity, high integration levels and higher operating speeds at all levels of integration (chip, MCM, printed circuit board and system). The growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and accordingly the design time. EMC is not commonly accepted as a vital topic in microelectronic design. Microelectronic designers often are of the opinion that EMC is limited to electrical and electronic systems and the mandatory product regulations instead of setting requirements also for the integrated circuit they are designing. In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into the system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be presented. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible.

In this paper, we propose two mechanisms for the priority added automatic call gapping method under the fairness scheme and analyze the effect of those mechanisms. Both mechanisms provide good overload controllability and work well on the priority calls. We also define a measure of priority achievement. Both mechanisms show good performance on the pass probability and priority achievement.