The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

The analysis of an architecture may provide statistic information on the use of the resources and on the execution time. Some of these information need just a static analysis. Others, such as the execution time, may need dynamic analysis. Moreover as the computation time of behavioral descriptions (control step time unit) and RTL ones (cycle based) may differ a lot, unexpected architectures may be generated by behavioral synthesis. Therefore means to debug the results of behavioral synthesis are required. This paper introduces a new approach to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The simulator and the behavioral synthesis are based on the same model. This model allows to link the behavioral description and the architecture produced by synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subexpressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.

In this paper, an efficient approach to the synthesis of CA (Cellular Architecture) -type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O (n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.

A CAD-based faulty portion diagnosis technique for CMOS-LSI with single fault using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducing the faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnomal Iddq. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal Iddq exists in the inner logic state with normal Iddq or not. The former block is regarded as normal block and the latter block is regarded as faulty block. Faulty portion of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours and reliable extraction of the faulty portion.

Nonuniform transmission lines are crucial in integrated circuits and printed circuit boards, because these circuits have complex geometries and layout between the multi layers, and most of the transmission lines possess nonuniform characteristics. In this article, an efficient numerical method for analyzing nonuniform transmission lines has been presented by using the Chebyshev expansion method and moment techniques. Efficiency on computational cost is demonstrated by numerical example.

We present theoretical results on the convergence of iterative methods for the solution of linear differential-algebraic equations arising form circuit simulation. The iterative methods considered include the continuous-time and discretetime waveform relaxation methods and the Krylov subspace methods in function space. The waveform generalized minimal residual method for solving linear differential-algebraic equations in function space is developed, which is one of the waveform Krylov subspace methods. Some new criteria for convergence of these iterative methods are derived. Examples are given to verify the convergence conditions.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

A modified cryptographic key assignment scheme for the dynamic access control in a group-oriented user hierarchy is presented. In the partially ordered set (poset, for short) user hierarchy (GjGi) embedded in a group-oriented (t, n) threshold cryptosystem, the source group Gi has higher security clearance to access the information items held in the target group Gj. If a target group Gj has multipe paths reachable from a source group Gi, we must choose the least cost path to rapidly resolve the dynamic access control problem Furthermore, multiple threshold values are also considered in order to meet the different security requirements.

In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

In this paper, we first prove that the Randomly Addressed Polling (RAP) protocol is unstable under the random access channel with heavy traffic. We also show that network stability can be ensured by controlling the arrival rate λ or by expanding the available addresses p on the assumption that there are M finite stations within the coverage of the controller (the base station). From analyses and results, we see the equilibrium of arrival rate is inversely proportional to the product of users (stations) and the exponent of stations. We also see that the maximum throughput can be derived at the point of λ1/M. This maximum performance can be easily obtained under the consideration of RAP protocol's stability. It also implies that the maximum throughput is independent of the available addresses of RAP protocol when pM.

To implement the PGPS packet scheduling algorithm in high speed networks is more difficult since it is based on real time simulation of an equivalent fluid-model system leading to a higher implementation time complexity. A modified approach to PGPS is the SCFQ scheme. This scheme is easy to implement, but has an increasing end-to-end delay bound. The VC packet scheduling algorithm provides the same end-to-end delay bound as PGPS does, but has the disadvantage of unfairness. As SCFQ, SFQ is much easier to implement than PGPS and achieves the same fairness, but has a higher end-to-end delay bound than PGPS. We propose a new packet scheduling algorithm, called Minimum Starting-tag Fair Queueing (MSFQ), which assigns the virtual time to be the minimum starting tag over all backlogged connections. MSFQ is much easier to implement than PGPS and provides the same end-to-end delay bound for each connection and fairness as PGPS. In this paper, we will show the end-to-end delay bound and fairness of MSFQ and compare 5 rate-based packet scheduling algorithms including PGPS, VC, SCFQ, SFQ, and MSFQ focusing on end-to-end delay bound, fairness, and implementation time complexity.

The necessary and sufficient conditions for f (x2+x+1) and f (x2+x) to be irreducible, when f (x) is irreducible, are proved. A method that produces polynomials whose roots are linearly independent (therefore form a normal basis for a finite field) is presented.

A novel cryptographic key assignment scheme for dynamic access control in a user hierarchy is presented. Based on Rabin's public key system and Chinese remainder theorem, each security class SCi is assigned a secret key Ki and some public parameters. In our scheme, a secret key is generated in a bottom-up manner so as to reduce the computation time for key generation and the storage size for public parameters. We also show that our proposed scheme is not only secure but also efficient.

Connectionless data from existing network applications compose a large portion of the workload during an early ATM deployment, and are likely to make up an important portion of ATM's workload even in the long term. For providing a connectionless service over the ATM network, we compare two approaches; an indirect and a direct approaches, which are adopted by International Telecommunication Union-Telecommunication (ITU-T) as generic approaches. Our main subject of this paper is to compare network costs of two approaches by taking into account several cost factors such as transmission links, buffers, and connectionless servers in the case of the direct approach. Since the cost of the direct approach heavily depends on the configuration of a virtual connectionless overlay network, we propose a new heuristic algorithm to construct an effective connectionless overlay network topology. The proposed algorithm determines an optimal number of connectionless servers and their locations to minimize the network cost while satisfying QoS requirements such as maximum delay time and packet loss probability. Through numerical examples, we compare the indirect and direct approaches, the latter of which is constructed by means of our proposed algorithm.

This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation methods is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 105 cycles write/erase operation is more than 10 times longer in comparison with the conventional method. This memory cell by using the proposed write/erase operation method has superior potential for application to 256 Mbit Flash memories as beyond.