Polarization transformation characteristics of a statified slab consisting of uniaxial chiral layers are investigated. It is assumed that a plane electromagnetic wave with arbitrary polarization is normally incident from free space on the stratified slab, which is located on a dielectric substrate. Note that the electric field inside a uniaxial chiral layer is expressed as a sum of four plane waves with different wavenumbers. The wavenumbers are found by seeking non-trivial solutions of the constitutive relations with Maxwell's equations. The electric field components of the transmitted and reflected waves can be obtained from a chainmatrix formalism. The powers and the Stokes parameters of the two waves are represented in terms of their electric field components. As is well known, the Stokes parameters uniquely describe every possible state of polarization of a plane wave. Numerical results are presented for two types of uniaxial chiral structure. The cross- and co-polarized powers and the Stokes parameters of the transmitted and reflected waves are computed for the incident plane wave of linear polarization. The results demonstrate a significant polarization transformation of the transmitted wave. Then it is shown that the stratified slab can be used as efficient polarization-transformation transmission filters active at some frequency band.

Bit-interleaving can enhance performance of a trellis coded modulation system over a fading channel. A combined system with decision feedback equalization is proposed. In the system, TCM decoded symbols are fed back for equalization. To avoid a bad effect of decoding delay, a deinterleaver is utilized effectively. Information sequence is divided into three subsequences and encoded by three encoders. Among the 3 code vectors from the encoders, bits are interleaved and decoding proceeds in parallel. Simulation results show that the proposed system realizes 0.6 dB more coding gain than a symbol interleaved system. A calculation method of a branch metric for decoding is proposed. Performance with the branch metric is shown to be nearly independent from the desired/undesired power ratio of a intersymbol interference channel. An approximate upper bound is analyzed for the proposed system, and the optimum code is searched.

This paper describes an efficient and simple coding algorithm of universally optimal codes for stationary (ergodic) sources and noiseless channel with unequal symbol costs. The symbol cost indicates the required time (or space) for the transmission (or storage) of that symbol, and the cost of any code symbol depends only on that symbol. The proposed coding algorithm mainly consists of two parts. The first part is based on the well-known Ziv-Lempel coding algorighm proposed in 1978 (sometimes called LZ78), and the second part is based on the Varn coding algorithm. The coding algorithm asymptotically achieves an optimal average cost of codes for stationary sources, and also achieves an optimal cost of codes for stationary ergodic sources with probability one. Furthermore, the computational complexity of the proposed coding algorithm is linear with respect to the length of source sequence and coded sequence.

Generalized minimum-distance (GMD) decoding is well-known as a soft decision decoding technique for such linear block codes as BCH and RS codes. The GMD decoding algorithm generates a set of candidate codewords and selects as a decoded codeword that candidate with the smallest reliable distance. In this paper, for a GMD decoder of RS and BCH codes, we present a new sufficient condition for the decoded codeword to be optimal, and we show that this sufficient condition is less stringent than the one presented by Taipale and Pursely.

We consider methods to locate sync words in packet or frame transmission over the additive white Gaussian noise channel. Our starting point is the maximization of the probability of correctly locating the sync word. We extend Massey's original result to the specific synchronization problem, where the sync words is prefixed to the data stream and each packet is preceded by idle transmission or additive white Gaussian noise. We give simulation results for several interesting sync words such as Barker sequences of length 7 and 13 and a sync word of length 17 with good cross-correlation properties. One of the conclusions is that the newly derived formula for the probability of correctly locating the sync word enables the reduction of the false sync detection probability.

In recently year, the analysis of power management becomes more important. It is difficult to obtain the maximum power because this is NP-complete. For an n-input circuit, there are 22n different input patterns to be considered. There are two major methods for this problem. First method is to generate input patterns to obtain the maximal power by simulating these generated patterns. This method is called pattern based. The other one uses probability method to estimate the power density of each node of a circuit to calculate the maximal power. In this paper, we use a pattern based method to estimate the maximal power. This method is better than that of probability for the simulation of power activity. In practical applications, these generated patterns can be applied and observe the activity of a circuit. These simulated data can be used to examined the critical paths for performance optimization. A simulated annealing algorithm is proposed to search input patterns for maximum power. Firstly, it transforms this problem into an optimization problem to adapt the simulated annealing method. In this method, there are three strategies for generating the next input patterns, called neighborhood. In the first strategy, it generates the next input pattern by changing the status of all input nodes. In the second strategy, some input nodes are selected and changed randomly.

In the paper the well known ray method is generalized to the case of the inhomogeneous chiral electromagnetic media. The electromagnetic field decompose in a chiral medium into two components with different propagation velocities. In the paper each of these components are presented in the form of ray expantions. The coefficients of these expantions are calculated in the ray coordinates which are attributed to the characteristics of eikonal equations. The leading and admixed components of the electromagnetic vectors are investigated and the polarization effects for both field components are analysed.

A method for analyzing the scattering of electromagnetic waves by a general bianisotropic slab is presented by extending the author's previous approaches for anisotropic, chiral, and those periodic media. The analysis is formulated in a unified matrix form, so that scattering characteristics can be obtained by system matrix calculations. The method can be extended straightforwardly to multilayerd and periodic structures. The scattering efficiencies are obtained for the incidence of not only linearly polarized waves but also circularly polarized waves.

The electric field intensity of the THz radiation from YBCO thin films excited by ultrashort laser pulses has been enhanced by a factor of 3 using a-axis oriented films instead of c-axis oriented ones used previously under the same excitation conditions. This corresponds to the enhancement of a factor of 10 for the radiation power. From the transmittance measurements of the millimeter wave for a-and c-axis oriented films, the origin of the enhancement is attributed to the increased fraction of the THz electromagnetic wave power transmitted from the YBCO film to free space. This result indicates that the utilization of the anisotropic properties of high-Tc superconductors is effective to enhance the radiation power.

In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Look Up Table) sets to be placed. In each bipartitioning, the algorithm first searches the paths with tighter path length constraints by estimating their path lengths. Second the algorithm proceeds the bipartitioning so that the path lengths of critical paths can be reduced. The algorithm is applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm satisfies the path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

For the completely polarized wave case, this paper presents the explicit formulae of the characteristic polarization states in the co-polarized radar channel, from which one can obtain the CO-POL Max, the CO-POL Saddle and the CO-POL Nulls in the Stokes vector form. Then the problem on the polarimetric contrast optimization is discussed, and the explicit formula of the optimal polarization state for contrast enhancement is presented in the Stokes vector form for the first time. To verify these formulae, we give some numerical examples. The results are completely identical with other authors', which shows the validity of the presented method.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.

Minato has proposed canonical representation for polynomial functions using zero-suppressed binary decision diagrams (ZBDDs). In this paper, we extend binary moment diagrams (BMDs) proposed by Bryant and Chen to handle variables with degrees higher than l. The experimental results show that this approach is much more efficient than the previous ZBDDs' approach. The proposed approach is expected to be useful for various problems, in particular, for computer algebra.

This paper proposes a heuristic algorithm for state minimization of incompletely specified finite state machines (FSMs). The strategy is similar to that in ESPRESSO, a wellknown heuristic algorithm for two-level logic minimization. It consists of generating an initial solution, the set of maximal compatibles, and attempting to apply a series of transformations to the solution. The main transformation is to reduce each compatible in the solution and delete unnecessary compatibles by iterative improvements. Other transformations, such as expansion and merging of compatibles, are also introduced for further reduction. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a Binary Decision Diagram. Experimental results show that the proposed method finds better solutions in shorter CPU times for most of the examples than conventional methods.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

New THz radiation devices made of high-Tc superconductors are fabricated and their characteristics are studied in detail. Ultrashort electromagnetic pulses with 0.5 ps width have been radiated into free space from current biased devices made of superconducting YBa2Cu3O7 (YBCO) films by exciting with femtosecond laser pulses. The Fourier spectrum of them extends up to 3 THz. The radiation mechanism is ascribed to the ultrafast supercurrent modulation by the optical pulses. The THz waveform is analyzed using rate equations describing the relaxation of photoexcited quasiparticles. By the improvement of the device structure and the collecting optics, the radiation power can be increased up to 0.5 µW. A new type THz radiation from YBCO films under an external magnetic field without a transport current is also reported.

We report on progress in the development of high-current-density all-NbN tunnel junctions for application as submillimeter wave SIS mixers. A very high current density up to 54 kA/cm2, roughly an order of magnitude larger than any reported results for all-NbN tunnel junctions, was achieved in the junctions with a thin aluminum nitride (AIN) tunnel barrier. Even though the junctions have a very high current density, they showed high-quality junction characteristics with a large gap voltage, sharp quasipartical current rise, and small subgap leakage current. The junctions also exhibited good Josephson tunneling behavior, excellent terahertz response, and sensitive heterodyne mixing properties. NbN/AIN/NbN tunnel junctions were integrated with a NbN thin-film antenna to investigate the terahertz responses and the heterodyne mixing properties in a quasioptical mixer testing system. Photon-assisted tunneling steps were clearly observed on the I-V curve with irradiation up to 1 THz, and low-noise heterodyne mixing was demonstrated in the 300-GHz band.

Ferroelectric / superconducting heterostructures of Pb(Zr0.52Ti0.48)O3 [PZT] / (Y0.6Pr0.4)Ba2Cu3Oy [YPBCO] have been formed on SrTiO3(100) substrate using an ArF pulsed laser deposition. The crystallinity and surface morphology of heterostructures were investigated by X-ray diffraction measurements and atomic force microscopy. We also measured dielectric and ferroelectric properties of PZT film in the Au/PZT/YPBCO structure. Furthermore, we fabricated a three-terminal devices having the structure described above using an in-situ metal mask exchange system, and investigated the ferroelectric field effect. As a result, we observed a modulation of channel resistance approximately equal to that estimated from the induced carrier and memory effect due to remanent polarization of PZT.