To construct the future multimedia network, ATM network technology and services should support cost-effective, high-speed interconnectivity and a variety of service-providing functions. Furthermore, as the infrastructure of future multimedia service, the ATM architecture should be adaptable to changes without needing replacement of its core functions and platform capabilities. This paper presents an overview of the current state of development, standardization and deployment of the ATM network service technologies and architecture concept. It also discusses the trend toward the integration of ATM technology and Internet technology. Also reported is the state of development and standardization for the individual ATM technologies and related issues, including access networks, bearer services, signalling, network middleware, and future ATM switching system technology.

A 2-GHz monolithic Si-bipolar logarithmic/ limiting amplifier is described. It features a waveform-dependent current phase shifter that compensates for the intrinsic dependence of unit-amplifier phase shifts on input signal amplitudes and layout techniques that minimize crosstalk in Si substrate. The amplifier dissipates 250 mW at a 3-V supply, which is less than 1/4 of that of previously reported ICs. The dynamic range of a received signal strength indicator (RSSI) is 60 dB and the limited-output phase deviation is less than 7 deg. at 2 GHz. Therefore, this amplifier is quite suitable for single-conversion transceivers for broadband wireless access systems.

This paper presents a new self-organization classification algorithm for remote-sensing images. Kohonen and other scholars have proposed self-organization algorithms. Kohonen's model easily converges to the local minimum by tuning the elaborate parameters. In addition to others, S. C. Amatur and Y. Takefuji have also proposed self-organization algorithm model. In their algorithm, the maximum neuron model (winner-take-all neuron model) is used where the parameter-tuning is not needed. The algorithm is able to shorten the computation time without a burden on the parameter-tuning. However, their model has a tendency to converge to the local minimum easily. To remove these obstacles produced by the two algorithms, we have proposed a new self-organization algorithm where these two algorithms are fused such that the advantages of the two algorithms are combined. The number of required neurons is the number of pixels multiplied by the number of clusters. The algorithm is composed of two stages: in the first stage we use the maximum self-organization algorithm until the state of the system converges to the local-minimum, then, the Kohonen self-organization algorithm is used in the last stage in order to improve the solution quality by escaping from the local minimum of the first stage. We have simulated a LANDSAT-TM image data with 500 pixel 100 pixel image and 8-bit gray scaled. The results justifies all our claims to the proposed algorithm.

The act of finding or constructing a model for a portion of a given polynomial or Bezier parametric surface from the whole original one is an encountered problem in surface modeling. A new method is described for constructing polynomial or Bezier piecewise model from an original one. It is based on the "Parametric Piecewise Model," abbreviated to PPM, of curve representation. The PPM representation is given by explicit expressions in terms of only control points or polynomial coefficients. The generated piecewise model behaves completely as a normal, polynomial or Bezier model in the same way as the original one for the piece of region considered. Also it has all characteristics, i. e, order and number of control points as the original one, and satisfies at the boundaries all order continuities. The PPM representation permits normalization, piecewise modeling, PPM reduction and systematic processes.

Considering the pattern classification/recognition tasks, the influence of the activation function on fault tolerance property of feedforward neural networks is empirically investigated. The simulation results show that the activation function largely influences the fault tolerance and the generalization property of neural networks. It is found that, neural networks with symmetric sigmoid activation function are largely fault tolerant than the networks with asymmetric sigmoid function. However the close relation between the fault tolerance and the generalization property was not observed and the networks with asymmetric activation function slightly generalize better than the networks with the symmetric activation function. First, the influence of the activation function on fault tolerance property of neural networks is investigated on the XOR problem, then the results are generalized by evaluating the fault tolerance property of different NNs implementing different benchmark problems.

In this paper, we propose a new type of authentication system, one-time zero-knowledge authentication system. Informally speaking, in this authentication system, double usage of the same authentication is prevented. Based on these one-time zero-knowledge authentication systems, we propose a new untraceable electronic cash scheme satisfying both untraceability and unreusablity. This scheme overcomes the problems of the previous scheme proposed by Chaum, Fiat and Naor through its greater efficiency and provable security under reasonable cryptographic assumptions. We also propose a scheme, transferable untraceable electronic cash scheme, satisfying transferability as well as the above two criteria. Moreover, we also propose a new type of electronic cash, untraceable electronic coupon ticket, in which the value of one piece of the electronic cash can be subdivided into many pieces.

Fiat-Shamir's identification and signature scheme is efficient as well as provably secure, but it has a problem in that the transmitted information size and memory size cannot simultaneously be small. This paper proposes an identification and signature scheme which overcomes this problem. Our scheme is based on the difficulty of extracting theL-th roots modn (e. g.L=2 1020) when the factors ofnare unknown. We prove that the sequential version of our scheme is a zero knowledge interactive proof system and our parallel version reveals no transferable information if the factoring is difficult. The speed of our scheme's typical implementation is at least one order of magnitude faster than that of the RSA scheme and is relatively slow in comparison with that of the Fiat-Shamir scheme.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

This paper focuses on competitive learning algorithms for WTA (winner-take-all) networks which perform rotation invariant pattern classification. Although WTA networks may theoretically be possible to achieve rotation invariant pattern classification with infinite memory capacities, actual networks cannot memorize all input data. To effectively memorize input patterns or the vectors to be classified, we present two algorithms for learning vectors in classes (LVC1 and LVC2), where the cells in the network memorize not only weight vectors but also their firing numbers as statistical values of the vectors. The LVC1 algorithm uses simple and ordinary competitive learning functions, but it incorporates the firing number into a coefficient of the weight change equation. In addition to all the functions of the LVC1, the LVC2 algorithm has a function to utilize under-utilized weight vectors. From theoretical analysis, the LVC2 algorithm works to minimize the energy of all weight vectors to form an effective memory. From computer simulation with two-dimensional rotated patterns, the LVC2 is shown to be better than the LVC1 in learning and generalization abilities, and both are better than the conventional Kohonen self-organizing feature map (SOFM) and the learning vector quantization (LVQ1). Furthermore, the incorporation of the firing number into the weight change equation is shown to be efficient for both the LVC1 and the LVC2 to achieve higher learning and generalization abilities. The theoretical analysis given here is not only for rotation invariant pattern classification, but it is also applicable to other WTA networks for learning vector quantization.

This paper first investigates a relationship between inkdot-depth and inkdot-size of inkdot two-way alternating Turing machines and pushdown automata with sublogarithmic space, and shows that there exists a language accepted by a strongly loglog n space-bounded alternating pushdown automaton with inkdot-depth 1, but not accepted by any weakly o (log n) space-bounded and d (n) inkdot-size bounded alternating Turing machine, for any function d (n) such that limn [d (n)log n/n1/2] = 0. In this paper, we also show that there exists an infinite space hierarchy among two-way alternating pushdown automata with sublogarithmic space.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

The proposed high-power-factor converter is constructed with a flyback converter, and locates the energy-storage capacitor on the secondary side of the transformer. A high power-factor can be obtained without needing to detect any current, and the ZVS operation can be achieved without auxiliary switches. To make the best use of these advantages in the converter, ZVS operations and power-factor characteristics in the converter were analyzed. From the analytical results, the effective control method for achieving ZVS was examined. Using a bread-board circuit controlled by this method, a power-factor of 0.99 and a conversion efficiency of 88% were measured.

In this paper, we study and analyze the overall acquisition performance of the combined acquisition-tracking synchronization loop for direct-sequence spread-spectrum (DS-SS) signals in the presence of Doppler shift. We consider both the change of effective search rate and the impact on the detection probability due to Doppler for the acquisition loop. We also determine the acquisition behavior of the digital delay lock loop (DDLL) in the presence of code Doppler. As a result, the influence of the DDLL's acquiring capability on the complete acquisition process is investigated and some numerical results are presented to demonstrate the acquisition performances of this combined loop which are quite different from the previous reports.

In this paper, a simple frame synchronization system for M-ary Spread Spectrum (M-ary/SS) communication system is analyzed. In particular, synchronization performance, bit error rate performance, and Spread Spectrum Multiple Access (SSMA) performance are analyzed. The frame synchronization system uses the racing counters. The transmitted signal contains framing chips that are added to spreading sequences. In the receiver, the framing chips are detected from several frames. The authors have proposed the simple frame synchronization system that detects framing chips from consecutive 2 frames. In this system, as the number of framing chips increases, synchronization performance improves and bit error rate performance degrades. In this paper a frame synchronization system that improves bit error rate performance is treated and analyzed. As the rusult, when the number of reference frames is 3, the bit error rate is much improved than the conventional system.

Pre-decorrelation is a method of achieving orthogonalization between multiple signals on the forward link. This technique can achieve orthogonalization in a flat fading channel, however, the orthogonality does not clearly appear in a multipath fading channel because of interchip interference. In order to eliminate the effect of multipath and prevent interchip interference, multicarrier modulation can be employed. In this paper we propose a multicarrier pre-decorrelation technique which combines multicarrier modulation with pre-decorrelation. Computer simulation results show that the proposed technique can achieve orthogonalization in a multipath fading channel.

This paper proposes an analysis method of scaling-factor-quantization error in fractal image coding using a state-space approach with the statistical analysis method. It is shown that the statistical analysis method is appropriate and leads to a simple result, whereas the deterministic analysis method is not appropriate and leads to a complex result for the analysis of fractal image coding. We derive the output error variance matrix for the measure of error and define the output error variance by scalar quantity as the mean of diagonal elements of the output error variance matrix. Examples are given to show that the scaling-factor-quantization error due to iterative computation with finite-wordlength scaling factors degrades the quality of decoded images. A quantitative comparison of experimental scaling-factor-quantization error with analytical result is made for the output error variance. The result shows that our analysis method is valid for the fractal image coding.

This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization.

This paper extends left-incompatible term rewriting systems defined by Toyama et al. It is also shown that the functional strategy is normalizing in the class, where the functional strategy is the reduction strategy that finds index by some rule selection method and top-down and left-to-right lazy pattern matching method.

In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.

A wireless communications system with a transmission rate of 10 Mbit/s using Japanese ISM band (2471-2497 MHz) is presented. This system employs a novel spread spectrum multiple access method named "CFO-SS (Carrier Frequency Offset-Spread Spectrum)" method. In the CFO-SS system, a single PN code is commonly assigned to all the multiple carriers, and the frequency offset between the carriers is determined by the information symbol rate, which is small as compared with the spread bandwidth of the signal. Bit error rate performance of the proposed CFO-SS system under multipath environments is investigated by computer simulation, and the performance of the CFO-SS method is confirmed for wireless LAN systems using the 2.4 GHz ISM band.