Thermally-diffused expanded core (TEC) techniques brought the fibers with the mode fields expanded by thermal diffusion of core dopants. The techniques are effective to the reduction of splice or connection losses between the different kind of fibers, and are applied to the integrations of thin film optical devices in fiber networks, the fabrications of chirped fiber gratings, and so on. In the practical use of TEC techniques, the fibers are heated high temperature of about 1650 because of a short peried of time in processing by microburners. The mode field diameter expansion (MFDE) ratio, which is defined as the ratio of the mode field diameter in the fiber section having the core expanded and that unexpanded, is desired to be more than 2.0 from the viewpoint of loss reduction in industrial uses of the TEC techniques. When the TEC techniques are applied to polarization-maintaining optical fibers (PM fibers), such as PANDA fibers, both core dopants and stress applying part (SAP) dopants diffuse simultaneously. So the MFDE ratio is less than two without mode field deformation in conventional PANDA fibers which are practically used as PM fibers. In this paper a PANDA fiber design suitable for the TEC techniques is newly proposed. The fiber has 1.28 µm cutoff wavelength and the mode field diameter is about 11 µm before core expansion at 1.3µm wavelength.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

RF integration, until recently the integration of active devices in conventional architectures suitable for discrete-component circuits, is now turning into full-integration based on new architectures developed specifically for an LSI technology. This paper reviews some of the key existing and emerging circuit techniques and discusses the serious problem of crosstalk. In order to develop miniature and low power RF transceivers, direct-conversion and monolithic VCO's will be further studied. Silicon bipolar technology will still be playing major role beyond the year 2,000, and CMOS will also be used in certain applications.

A new method to obtain the coefficients of Daubechies's scaling functions is given, in which it is not necessary to find the complex zeros of polynomials. Consequently it becomes easier to obtain the coefficients of arbitrary order from 2 to 40 with high accuracy.

Highly parallel scalable multiprocessing systems (HMPs) are powerful tools for solving large-scale scientific and engineering problems. However, these machines are difficult to program since algorithms must exploit locality in order to achieve high performance. Vienna Fortran was the first fully specified data-parallel language for HMPs that provided features for the specification of data distribution and alignment at a high level of abstraction. In this paper we outline the major elements of Vienna Fortran and compare it to High Performance Fortran (HPF), a de-facto standard in this area. A significant weakness of HPF is its lack of support for many advanced applications, which require irregular data distributions and dynamic load balancing. We introduce HPF +, an extension of HPF based on Vienna Fortran, that provides the required functionality.

A factorization method for a string polynomial called the constant method is proposed. This uses essentially three operations; classification of monomials, gcrd (greatest common right divisor), and lcrm (least common rigth multiple). This method can be applied to string polynomials except that their constants cannot be reduced to zeros by the linear transformation of variables. To factorize such excluded string polynomials, the naive method is also presented, which computes simply coefficients of two factors of a given polynomial, but is not efficient.

A method of planar curve classification, which is invariant to rotation, scaling and translation using the zerocrossings representation of wavelet transform was introduced. The description of the object is represented by taking a ratio between its two adjacent boundary points so it is invariant to object rotation, translation and size. Transforming this signal to zero-crossings representation using wavelet transform, the minimum distance between the object and model while shifting the signals each other, can be used as classification parameter.

An alternative defuzzification technique for center of gravity calculation is proposed. The technique allows evaluation of fuzzy inferences without the use of multiplication. In fuzzy logic controllers with many outputs, the proposed scheme reduces the circuit complexity compared with other implementations.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

The maximal linear forest problem is to find, given a graph G = (V, E), a maximal subset of V that induces a linear forest. Three parallel algorithms for this problem are presented. The first one is randomized and runs in O(log n) expected time using n2 processors on a CRCW PRAM. The second one is deterministic and runs in O(log 2n) timeusing n4 processors on an EREW PRAM. The last one is deterministic and runs in O(log 5n) time using n3 processors on an EREW PRAM. The results put the problem in the class NC.

In this paper we extend the p-collection problem to a flow network with lower bounds, and call the extended problem the lower-bounded p-collection problem. First we discuss the complexity of this problem to show NP-hardness for a network with path structure. Next we present a linear time algorithm for the lower-bounded 1-collection problem in a network with tree structure, and a pseudo-polynomial time algorithm with dynamic programming type for the lower-bounded p-collection problem in a network with tree structure. Using the pseudo-polynomial time algorithm, we show an exponential algorithm, which is efficient in a connected network with few cycles, for the lower-bounded p-collection problem.

Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.

The first optimizing compiler was developed at IBM in order to prove that high level language programming could be as efficient as hand-coded machine language. Computer architecture and compiler optimization interacted through a feedback loop, from the high-level language computer architectures of the 1970s to the RISC machines of the 1980s. In the supercomputing community, the availability of effective vectorizing compilers delivered easy-to-use performance in the 1980s to the present. These compilers were successful at least in part because they could predict poor performance spots in the program and report these to users. This fostered a feedback loop between programmers and compilers to develop high performance programs. Future optimizing compilers for high performance computers and supercomputers will have to take advantage of both feedback loops.

We describe our implementation of the Hypercube variation of the Multiple Polynomial Quadratic Sieve (HMPQS) integer factorization algorithm on a Parsytec GC computer with 128 processors. HMPQS is a variation on the Quadratic Sieve (QS) algorithm which inspects many quadratic polynomials looking for quadratic residues with small prime factors. The polynomials are organized as the nodes of an n-dimensional cube. We report on the performance of our implementations on factoring several large numbers for the Cunningham Project.

We propose an improved orthogonal frequency division multiplexing (OFDM) signal detector which uses the minimum mean-square error (MMSE) noise feedback equalization (NFE). The input bit stream is trellis-coded to form OFDM signal blocks and the maximal ratio combining (MRC) is adopted at the receiver in order to improve the performance of the detector. As a result, we obtain significantly improved detection performance compared with the conventional OFDM receivers as follows. Using the proposed MMSE-NFE in the receiver, we can obtain the performance gain of about 1.5 dB to 2 dB in symbol energy to noise power spectral density (Es/No) for Doppler frequencies of fd=20 and 100 Hz, respectively, over the receiver with the MMSE linear equalization (LE) alone at symbol error rate (SER) of about 10-3. With MRC and trellis coding, the performance gain of about 11 dB in Es/No for fd=20 and 100 Hz at SER of about 10-3 is obtained.

A new numerical technique, termed the method of matrix-order reduction (MMOR), is developed for handling electromagnetic problems in this paper, in which the matrix equation resulted from a method-of-moments analysis is converted either to an eigenvalue equation or to another matrix equation with the matrix order in both cases being much reduced, and also, the accuracy of solution obtained by solving either of above equations is improved by means of a newly proposed generalized Jacobian iteration. As a result, this technique enjoys the advantages of less computational expenses and a relatively good solution accuracy as well. To testify this new technique, a number of wire antennas are examined and the calculated results are compared with those obtained by using the method of moments.

This paper presents intelligent memory, a new memory architecture capable of providing efficient lock-free synchronization. In the intelligent memory, a sequence of operations on a shared object associated with that memory module can be processed without any intervention so that an environment for the synchronization can be provided by executing a critical section itself in that memory module. For this, we present a memory architecture for the intelligent memory having minimal instruction set and develop a progtramming model, called Critical Section Procedure (CSP), which consists of shared data structures and operations on them. Intelligent memory is intended to eliminate waste of processing time such as busy waiting in spin lock and the retry due to process contentions in existing lock-free synchronization schemes. Simulation results show that the intelligent memory provides better throughput compared with the spin lock and the existing lock-free synchronization schemes.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

We developed a 1200 dots-per-inch light emitting diode array (1200 dpi LED array) chip using a GaAs0.8 P0.2 epitaxial substrate for the first time. One LED array chip consists of 256 LEDs. In general, LED arrays are fabricated by vapor-phase zinc diffusion. From the viewpoint that shallow junctions should be formed to fabricate a very high-density LED array, solid-phase diffusion seems to be more suitable. We fabricated the LED array using selectively-masked solid-phase zinc diffusion, and the diffusion depth was controlled at 1 µm. The diffusion depth was uniform under the diffusion window. The ratio of the length of lateral diffusion to the diffusion depth was about 1.7. These features imply that Zn diffusion was well controlled. In the Zn diffusion, the carrier concentration in the Zn diffusion region was high enough and the sheet resistance of the diffusion region with a diffusion depth of 1 µm was low enough to obtain a sufficient level of emitted light power. The results of performance tests showed that the characteristics of the LED array chip are satisfactory for application in optical printer print heads, because of the array's highly-resolved near-field pattern characteristic, ample emitted light power, low emitted-light-power deviation, and long life.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.