A multimedia content is usually read-only and composed of multimedia objects with their spatial and temporal specifications. These specifications given by its author can enforce the display of objects to be well organized for its context. When multimedia contents are serviced in network environment by an on-demand basis, the temporal relationship among the objects can be used to improve the performance of the service. This paper models the temporal relationship as a scenario that represents the presentation order of the objects in a scenario and proposes several scheduling methods that make it possible to rearrange the transmission order of objects in a scenario. As a result, system resources such as computing power and network bandwidth can be highly utilized. Since the temporal relationship of a scenario is static, it is possible to reduce the scheduling overhead of a server by pre-scheduling currently servicing scenarios. In addition, several simulation results are presented in order to compare and analyze the characteristics of the proposed methods.

CAM (Content Addressable Memory) units are generally designed so that they can be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application program written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

The Internet is a heterogeneous and rapidly evolving environment. New information services have been added, modified, and diversified, while legacy services have been abandoned. Users' requirements for services are also changing very quickly. It is becoming very difficult to find required information services from extremely huge amount of information in the Internet. It is necessary to design information service system, which can meet user's heterogeneous requirements for services, adaptability of services to cope with ever-changing situation and to provide assurance. Faded information field architecture and Push/Pull Mobile Agent (MA) technologies are proposed as basic components of autonomous information service system to achieve these goals. The system is proposed from users' and providers' point of view, therefore we present a technique for balancing users' and providers' communication cost based on `through rate' for faded information field realization. On the basis of this technique, autonomous information allocation algorithm is proposed, in which each node may determine information amount based on push/pull cost. The effectiveness of the proposed algorithm is shown through simulation.

Efficient content-based retrieval of complex images is a challenging task since the detected object may appear in various scale, rotation and orientation with a wide variety of background colors and forms. In this paper, we propose a novel representation of objects with multiple colors, the spatial neighborhood-adjacency graph(SNAG), which can serve as a basis for detecting object by color contents from the candidate image. The SNAG consists of a set of main-vertices and two sets of edges. Each main-vertex represents a single color region of multi-colored object, and edges are divided into two classes: Neighborhood edges representing neighborhood relationship between two main-vertices with similar color, and adjacency edges representing adjacency relationship between a main-vertex and another vertex with different color. By investigating whether SNAG of object image is an isomorphic subgraph of SNAG of a candidate image, we can determine whether the similar object exists in the candidate image. In addition, we have also applied the proposed approach to a range of different object detection problems involving complex background, and effectiveness has been proved.

A content-based image retrieval scheme based on scale-space theory is proposed. Instead of considering all scales for image retrieval, the proposed algorithm utilizes a modified histogram intersection method to compute the relative scale between a query image and a candidate image. The proposed method has been applied to various images and the performance improvement has been verified.

This paper evaluates the performance of a reliable multicast protocol for bulk-data transfer over unreliable networks via IP-multicast. Bulk-data type reliable multicast appears promising for commercial publishing and large-scale data replication. The proposed reliable multicast transport protocol (RMTP) provides high-performance due to the use of IP multicast while also providing confirmed and error free transfer by end-to-end controls. The protocol includes a multi-round selective repeat scheme dedicated for bulk-data multicast applications. This paper examines the multicast retransmission procedures in RMTP through analysis and tests on an implemented system and clarifies the basic performance behavior of the protocol. Evaluations are conducted with regard to retransmission redundancy, transfer time, and packet processing load with various error conditions and number of receivers. Against the response concentration problem seen in end-to-end communication, the backoff time algorithm is applied to the protocol; the limits it places on system scalability are clarified.

This paper proposes a medium access control (MAC) protocol for single-hop WDM star-coupler networks, in which the number of stations is larger than the number of channels and the stations have arbitrary distances to the star coupler. The proposed protocol has one control channel for reserving the slots of data channels and several data channels which are used to transmit traffic. This paper also suggests a scheme that accomplishes load balancing among data channels for arbitrary traffic patterns between stations. Since this load balancing scheme diminishes an influence that traffic patterns have on the performance of the proposed MAC protocol, the proposed system is appropriate for systems which have asymmetric traffic intensity between stations. Throughput and mean message delay of the MAC protocol are analyzed using a discrete time Markov process and a D/G/1 queue with batch arrivals. The numerical results show that the performance is improved as the message length increases, the maximum round-trip propagation delay decreases, and the number of data channels increases.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

An architecture is presented for efficient and reliable delivery of multimedia contents from a primary center (PC) to secondary centers (SCs). Requested contents are delivered from the PC to the SCs through a satellite broadcast channel, or from one SC to another SC through a terrestrial channel. Cycling methods are presented that enable sharing of the contents directory of each SC. Several fundamental models and algorithms are introduced for possible consideration during the planning and design of a contents-delivery system. Simulation has shown that using both satellite broadcast and terrestrial channels for contents delivery is superior in terms of cost to the conventional use of only a satellite network.

In order to lessen overflow or underflow problem in numerical computation, several new floating-point arithmetics have been proposed. The significant advantage of these new arithmetics is that a number can be represented in a wider range since the fields of exponent and mantissa are changed depending on the magnitude of number. The main issues of these arithmetics are how to find the boundary between exponent and mantissa as well as to convert the formats between new floating-point arithmetic and fixed-point arithmetic quickly. In this paper, a CAM-based array converter based on the Universal Representation of Real number (URR) floating-point arithmetic is described. Using match retrieval device CAM, the detection of the boundary can be accomplished faster than conventional circuits. Arranging the basic cells into iterative array structure, the fast separation/connection operation is achieved. The speed, area and power consumption of the converter is estimated.

The next generation mobile communications systems must support multimedia communications services as well as conventional voice service. DS-CDMA is regarded as the most promising candidate, because it is indispensable to cope with multimedia. The system capacity of DS-CDMA system is limited by the total interference level. As a result, in DS-CDMA systems many users suffer very poor communication quality if the total interference level exceeds this limit. Therefore, this paper considers smoothing interference fluctuation using the difference between voice and data in a type of QoS (quality of service). In other words, voice communication is suitable for a loss system because the quality of voice communication is delay-sensitive. On the other hand, data communication is suitable for a waiting system because the quality of data communication is non-delay-sensitive. This paper focuses on a system that applies a circuit switching method for voice traffic and a reservation type packet switching method for data traffic and proposes a data traffic control method. In this proposed data traffic control method, a base station controls data transmission from a mobile station to utilize unused voice traffic resources. As a result, the proposed method achieves highly efficient use of the radio spectra by smoothing interference fluctuation in DS-CDMA systems. This paper evaluates the performance level of the proposed method from a system capacity standpoint. It is shown that the proposed method achieves higher system capacity in voice/data integrated transmission.

An analysis is carried out about the reflection influence on the microwave attenuation measurement for moisture content determination. A new method taking into account the reflection influence is proposed and it is proved valid by the experiment results. Using this method, the density dependence of the attenuation is measured and the measured data can be fitted well by a straight line passing through the origin. Therefore, the attenuation per unit density and propagation distance is a function which depends only on the moisture content and the function is useful to the determination of the moisture content.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

Research in very low-bit rate coding has made significant advancements in the past few years. Most recently, the introduction of the MPEG-4 proposal has motivated a wide variety of a approaches aimed at achieving a new level of video compression. In this paper we review progress in VLBV categorized into 3 main areas. (1) Waveform coding, (2) 2D Content-based coding, and (3) Model-based coding. Where appropriate we also described proposals to the MPEG-4 committee in each of these areas.

This paper describes methods in which natural language is used to describe video contents, knowledge of which is needed for intelligent video manipulation. The content encoded by natural language is extracted by a language analyzer in the form of subject-centered dependency structures which is a language-oriented structure, and is combined in an incremental way into a single structure called a multi-path index tree. Content descriptors and their inter-relations are extracted from the index tree in order to provide a high speed retrieval and flexibility. The content-based video index is represented in a two-dimensional structure where in the descriptors are mapped onto a component axis and temporal references (i.e., video segments aligned to the descriptors) are mapped onto a time axis. We implemented an experimental image retrieval systems to illustrate the proposed index structure 1) has superior retrieval capabilities compare to those used in conventional methods, 2) can be generated by an automated procedure, and 3) has a compact and flexible structure that is easily expandable, making an integration with vision processing possible.

CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE --the CAM-based hardware engine developed in our laboratory--are also reported.

This paper proposes a new stochastic language model for speech recognition based on function-word N-grams and content-word N-grams. The conventional word N-gram models are effective for speech recognition, but they represent only local constraints within a few successive words and lack the ability to capture global syntactic or semantic relationships between words. To represent more global constraints, the proposed language model gives the N-gram probabilities of word sequences, with attention given only to function words or to content words. The sequences of function words and of content words are expected to represent syntactic and semantic constraints, respectively. Probabilities of function-word bigrams and content-word bigrams were estimated from a 10,000-sentence text database, and analysis using information theoretic measure showed that expected constraints were extracted appropriately. As an application of this model to speech recognition, a post-processor was constructed to select the optimum sentence candidate from a phrase lattice obtained by a phrase recognition system. The phrase candidate sequence with the highest total acoustic and linguistic score was sought by dynamic programming. The results of experiments carried out on the utterances of 12 speakers showed that the proposed method is more accurate than a CFG-based method, thus demonstrating its effectiveness in improving speech recognition performance.

New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.

Since carelessness in driving causes a terrible traffic accident, it is an important subject for a vehicle to avoid collision autonomously. Real-time collision detection between a vehicle and obstacles will be a key target for the next-generation car electronics system. In collision detection, a large storage capacity is usually required to store the 3-D information on the obstacles lacated in a workspace. Moreover, high-computational power is essential not only in coordinate transformation but also in matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a Content-Addressable Memory (CAM) which evaluates the magnitude relationships between an input word and all the stored words in parallel. A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be parformed only by parallel magnitude comparison. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. The collision detection time becomes 5.2 ms using 20 PEs and five CAMs with a 42-kbit capacity.