A new radar system is presented, which consists of one main radar and cooperative plural transponders. The transponders are integrated in the respective retrodirective antennas which are arranged beyond the horizon in such a manner as they surround the main radar. An algorithm for determining the three-dimensional target position is given. Computer simulations have been made for different target positions by assuming measurement errors. A target whose monostatic radar cross section is small or has been specially reduced by absorbing materials could be detected by this system if it is properly constructed.

Subharmonically Injection-locked oscillators (ILO's) with very wide injection-locking ability are presented. Two types of ILO MMIC's with this ability are proposed. The oscillation frequency tuning function of the ILO MMIC is very useful for expansion of the injection locking range at higher subharmonics. One consists of a shunt varactor diode inserted into the oscillation loop, and the other incorporates a vector-combining configuration with in-phase divider and 90 degree hybrid. Using three-dimensional MMIC's technology which can offer miniature and high-density passive circuits, the vector-combining type ILO is formed in a very compact area of 1. 7 mm2. Fabricated 20 GHz-band ILO achieves a wide tuning ranges of 870 MHz, resulting in a very wide locking range for higher subharmonics. The wide frequency tuning ability also reduces phase noise, shortens a locking time and compensates the center frequency deviation against temperature, as well as increasing locking range. The measured results show that the ILO configuration is extremely suitable for realizing simple, fully monolithic and low phase noise millimeter-wave frequency synthesizers.

Two-dimensional (2-D) adaptive digital filters (ADFs) for 2-D signal processing have become a fascinating area of the adaptive signal processing. However, conventional 2-D FIR ADF's require a lot of computations. For example, the TDLMS requires 2N2 multiplications per pixel. We propose a new 2-D adaptive filter using the FFTs. The proposed adaptive filter carries out the fast convolution using overlap-save method, and has parallel structure. Thus, we can reduce the computational complexity to O(log2N) per pixel.

This paper describes a new high resolution algorithm for the two-dimensional (2-D) frequency estimation problem, which, in particular, is noise insensitive in view of the fact that in many practical applications the contaminated noise may not be white noise. For this purpose, the approach is set in the context of higher-order statistics (HOS), which has demonstrated to be an effective approach under a colored noise environment. The algorithm begins with the consideration of the fourth-order moments of the available 2-D data. Two auxiliary matrices, constituted by a novel stacking of the diagonal slice of the computed fourth-order moments, are then introduced and through which the two frequency components can be precisely determined, respectively, via matrix factorizations along with the subspace rotational invariance (SRI) technique. Simulation results are also provided to verify the proposed algorithm.

In this paper, we give a new approach to the computation of primary decomposition and associated prime components of a zero-dimensional polynomial ideal (f1,f2,. . . ,fn), where fi are multivariate polynomials on Z (the ring of integer). Over the past several years, a considerable number of studies have been made on the computation of primary decomposition of a zero-dimensional polynomial ideal. Many algorithms to compute primary decomposition are proposed. Most of the algorithms recently proposed are based on Groebner basis. However, the computation of Groebner basis can be very expensive to perform. Some computations are even impossible because of the physical limitation of memory in a computer. On the other hand, recent advance in numerical methods such as homotopy method made access to the zeros of a polynomial system relatively easy. Hence, instead of Groebner basis, we use the zeros of a given ideal to compute primary decomposition and associated prime components. More specifically, given a zero-dimensional ideal, we use LLL reduction algorithm by Lenstra et al. to determine the integer coefficients of irreducible polynomials in the ideal. It is shown that primary decomposition and associated prime components of the ideal can be computed, provided the zeros of the ideal are computed with enough accuracy. A numerical experiment is given to show effectiveness of our algorithm.

Time series prediction is very important technology in a wide variety of fields. The actual time series contains both linear and nonlinear properties. The amplitude of the time series to be predicted is usually continuous value. For these reasons, we combine nonlinear and linear predictors in a cascade form. The nonlinear prediction problem is reduced to a pattern classification. A set of the past samples x(n-1),. . . ,x(n-N) is transformed into the output, which is the prediction of the next coming sample x(n). So, we employ a multi-layer neural network with a sigmoidal hidden layer and a single linear output neuron for the nonlinear prediction. It is called a Nonlinear Sub-Predictor (NSP). The NSP is trained by the supervised learning algorithm using the sample x(n) as a target. However, it is rather difficult to generate the continuous amplitude and to predict linear property. So, we employ a linear predictor after the NSP. An FIR filter is used for this purpose, which is called a Linear Sub-Predictor (LSP). The LSP is trained by the supervised learning algorithm using also x(n) as a target. In order to estimate the minimum size of the proposed predictor, we analyze the nonlinearity of the time series of interest. The prediction is equal to mapping a set of past samples to the next coming sample. The multi-layer neural network is good for this kind of pattern mapping. Still, difficult mappings may exist when several sets of very similar patterns are mapped onto very different samples. The degree of difficulty of the mapping is closely related to the nonlinearity. The necessary number of the past samples used for prediction is determined by this nonlinearity. The difficult mapping requires a large number of the past samples. Computer simulations using the sunspot data and the artificially generated discrete amplitude data have demonstrated the efficiency of the proposed predictor and the nonlinearity analysis.

We present a finite-difference time-domain (FD-TD) method with the perfectly matched layers (PMLs) absorbing boundary condition (ABC) based on the multidimensional wave digital filters (MD-WDFs) for discrete-time modelling of Maxwell's equations and show its effectiveness. First we propose modified forms of the Maxwell's equations in the PMLs and its MD-WDFs' representation by using the current-controlled voltage sources. In order to estimate the lower bound of numerical errors which come from the discretization of the Maxwell's equations, we examine the numerical dispersion relation and show the advantage of the FD-TD method based on the MD-WDFs over the Yee algorithm. Simultaneously, we estimate numerical errors in practical problems as a function of grid cell size and show that the MD-WDFs can obtain highly accurate numerical solutions in comparison with the Yee algorithm. Then we analyze several typical dielectric optical waveguide problems such as the tapered waveguide and the grating filter, and confirm that the FD-TD method based on the MD-WDFs can also treat radiation and reflection phenomena, which commonly done using the Yee algorithm.

Recently reported multidimensional geometrically uniform signal constellations (L MPSK and Decomposed-Lattice constellations) are joined in the term of Generalized Permutation Alphabets (GPA). Possibility of a binary isometric labeling of GPA's is completely characterized. An algorithm for constructing generating groups of PSK-type GPA is proposed. We show that this concept, when is extended to the lattice, gives rise to a class of new coset codes which perform out best codes listed in [11].

Turbo codes have fascinated many coding researchers because of thier near-Shannon-limit error correction performance. In this paper, we discuss multi-dimensional turbo codes which are parallel concatenation of multiple constituent codes. The average upper bound to bit error probability of multidimensional turbo codes is derived. The bound shows that the interleaver gains of this kind of codes are larger than that of conventional two-dimensional turbo codes. Simplified structures of multi-dimensional turbo encoder and decoder are proposed for easier implementation. Simulation results show that for a given interleaver size, by increasing the dimension, great performance improvement can be obtained.

In this paper, we present a lower bound for the dimension of subfield subcodes of residue Goppa codes on the curve Cab, which exceeds the lower bound given by Stichtenoth when the number of check symbols is not small. We also give an illustrative example which shows that the proposed bound for the dimension of certain residue Goppa code exceeds the true dimension of a BCH code with the same code length and designed distance.

We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.

In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

This paper discusses a design method for two-dimensional (2-D) periodically time-variant digital filters (PTVDFs) whose filter coefficients vary periodically. First, 2-D periodicities for a variation of filter cefficients are considered, from which two and four-phase variations of coefficients are shown to be suitable for practical applications. Then, the input-output relation (transfer function) for 2-D separable-denominator (SD) PTV DFs is derived, which results in a linear combination of the baseband input signal and its modulated versions. Finally, in order ro approximate given filter specifications, the structure for 2-D SD PTV DFs is given and a design method is proposed. It is shown that, compared with the 2-D SD time-invariant DFs, approximation error can be reduced with the proposed SD PTV DFs.

A pipelined adaptive digital filter (ADF) architecture based on a two-dimensional least mean square algorithm is proposed. This architecture enables the ADF to be operated at a high clock rate and reduction of the required amount of hardware. To achieve this reduction we introduce a new building unit, called a block, and propose implementing the pipelined ADF using the block, Since the number of blocks in a cell is adjustable, we derive a condition for satisfying given specifications. We show the smallest number of blocks and the corresponding delay can be determined by using the proposed method.

In this paper, we propose a new strategy of estimating correlation dimensions in combination with the method of surrogate data, which is a kind of statistical control usually introduced to avoid spurious estimates of nonlinear statistics, such as fractal dimensions, Lyapunov exponents and so on. In the case of analyzing time series with the method of surrogate data, it is desirable to decide values of estimated nonlinear statistics of the original data and surrogate data sets as exactly as possible. However, when dimensional analysis is applied to possible attractors reconstructed from real time series, it is very dangerous to decide a single value as the estimated dimensions and desirable to analyze its scaling property for avoiding spurious estimates. In order to solve this defficulty, a dimension estimator algorithm and the method of surrogate data are combined by introducing Monte Carlo hypothesis testing. In order to show effectiveness of the new strategy, firstly artificial time series are analyzed, such as the Henon map with additive noise, filtered random numbers and filtered random numbers transformed by a static monotonic nonlinearity, and then experimental time series are also examined, such as wolfer's sunspot numbers and the fluctuations in a farinfrared laser data.

In this paper, we give a new lower bound for the dimension of subfield subcodes. This bound improves the lower bound given by Stichtenoth. A BCH code and a subfield subcode of algebraic geometric code on a hyper elliptic curve are discussed as special cases.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

In this paper, we propose a handoff scheme with two-level priority for the reservation of handoff request calls in mobile cellular radio systems. We assume two types of mobile subscribers with different distributions of moving speed, that is, users with low average moving speed (e.g., pedestrians) and high average moving speed (e.g., people in moving cars). A fixed number of channels in each cell are reserved exclusively for handoff request calls. Out of these number of channels, some are reserved exclusively for the high speed handoff request calls. The remaining channels are shared by both the originating and handoff request calls. In the proposed scheme, both kinds of handoff request calls make their own queues. The system is modeled by a three-dimensional Markov chain. We apply the Successive Over-Relaxation (SOR) method to obtain the equilibrium state probabilities. Blocking probabilities of calls, forced termination probabilities and average queue length of handoff calls of each type are evaluated. We can make the forced termination probabilities of handoff request calls smaller than the blocking probability of originating calls. Moreover, we can make the forced termination probability of high speed handoff request calls smaller than that of the low speed ones. Necessary queue size for the two kinds of handoff request calls are also estimated.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.