This letter describes an efficient and economical method for dropping optical fiber to residential premises in which several fiber ribbons in a distribution cable are assigned to one dropping point. The optical fiber cables for dropping, which contain mono-coated fibers, are then aerially installed between several poles from this point during initial construction. One or two fibers in a cable are then branched and dropped to a subscriber when the demand arises. When an optical drop wire stranded cable is used as the optical fiber cable for dropping, the above method can be employed without the need for a fiber joint in the dropping portion. The tube stranding pitch of this cable is investigated theoretically and experimentally, and the cable is manufactured based on the results. The transmission characteristics of the cable are confirmed to be stable.

We demonstrate a feasibility of a Beam Space CMA (Constant Modulus Algorithm) Adaptive array antenna by implementing a Digital Signal Processor (DSP) in ASICs using field programmable gate arrays (FPGA). The DSP can synthesize 16 multibeams and eliminate interference signals by CMA adaptive processing. The whole function was implemented in about 127,000 equivalent gates. Simple experimental results in a radio anechoic chamber have confirmed the basic function of BSCMA adaptive array antenna.

A down sampling technique was applied to signal processing of fiber optic gyroscopes with optical phase modulation. The technique shifts the frequency spectrum of the gyroscopic signal down to low frequencies, and lowers the speed requirements for analog-to-digital (A/D) conversion and numerical operations. A single-chip digital signal processor (DSP) with a built-in A/D converter and timers was used to demonstrate the proposed technique. The DSP internally generated a phase modulation signal and sampling trigger timing. The reference signals for digital lock-in discrimination of gyroscopic spectrum are generated by using an external binary counter, and their phases were adjusted optimally by DSP software. The DSP compensated for fluctuations in laser source intensity and phase modulation index, using the signal spectrum extracted, and linearized the gyroscopic response. The measured resolution of rotation detection was 0.9 deg/s (with a full scale of 100 deg/s) and it agreed with the resolution in A/D conversion.

This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm2 single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.

A description language for matrix and vector expressions and its compiler for DSPs are shown. They provide both a user-friendly programming environment and efficient codes. In order to increase throughput and to reduce amount of methods based on mathematical laws are introduced. A method to decide the matrix and vector storage location suitable for processing on DSP is also proposed.

In this paper, we present Branching Oriented System Equation based on-line error correction scheme for recursive digital signal processing. The target digital signal processing is linear and time-invariant, and the algorithm includes multiplications with constant coefficient, additions and delays. The difficulties of the algorithm-level fault tolerance for such algorithm without structural regularity include error distribution problem and right timing of error correction. To escape the error distribution problem, multiple fan-out nodes in an algorithm are specified as the nodes at which error corrections are performed. The Branching Oriented Graph and Branching Oriented System Equation are so introduced to formulate on-line correction schemes based on this strategy. The Branching Oriented Graph is treated as the collection of computation sub-blocks. Applying checksum code independently to each sub-block is our most trivial on-line error correction scheme, and it results in, with appropriate selection of error identification process, TMR in sub-block level. One of the advantages of our method is in the reduction of redundant operations performed by merging some computation sub-blocks. On the other hand, the schedulability of the system is an important issue for our method since our on-line error correction mechanism induces additional data dependencies. In this paper, the schedulability condition and some modifications on the scheme are also discussed.

This paper presents the M-LCELP (Multi-mode Learned Code Excited LPC) speech coder, which has been developed for the next generation half-rate digital cellular telephone systems. M-LCELP develops the following techniques to achieve high-quality synthetic speech at 4kb/s with practically reasonable computation and memory requirements: (1) Multi-mode and multi-codebook coding to improve coding efficiency, (2) Pitch lag differential coding with pitch tracking to reduce lag transmission rate, (3) A two-stage joint design regular-pulse codebook with common phase structure in voiced frames, to drastically reduce computation and memory requirements, (4) An efficient vector quantization for LSP parameters, (5) An adaptive MA type comb filter to suppress excitation signal inter-harmonic noise. The MOS subjective test results demonstrate that 4.075kb/s M-LCELP synthetic speech quality is mostly equivalent to that for a North American full-rate standard VSELP coder. M-LCELP codec requires 18 MOPS computation amount. The codec has been implemented using 2 floating-point dsp chips.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.