We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.

Phase locked loops (PLL's) are well known as a threshold extension demodulator for analogue FM signals. This capability may lead to the low bit error rate demodulation for digital FM signals. A PLL has also its native frequency tracking ability and is suited to the demodulation of the signals having large Doppler shifts, for example signals from Low Earth Orbit (LEO) satellites. In this paper, we study the demodulation scheme of Continuous Phase FSK (CPFSK) and Gaussian filtered MSK (GMSK) signals using a Digital Signal Processing type Digital PLL (DSP DPLL). First we propose a DSP DPLL completely equivalent to an Analog PLL (APLL). Next we adopt the sequence estimation scheme to compensate the Inter-Symbol Interference (ISI) associated with the finite loop bandwidth of the DSP DPLL. Through computer simulations it is clarified that the proposed DSP DPLL with sequence estimator can achieve better BER performance compared with the conventional Limiter Discriminator (LD) detection on the AWGN channel. We have also shown that the DSP DPLL with sequence estimator has excellent BER characteristics on Rician fading channels having actual large Doppler shifts.

A new type of Meteor Burst Communication (MBC) network is developed. Each unit of the network is based on a DSP board running a modem software. All the fundamental blocks and functions of a modem are implemented in software. Unlike hardware modems, this software modem has flexibility of system configuration and operation. The system implements adaptability in terms of modulation type (number of phases in MPSK) using a unique dynamic channel estimation scheme appropriate for MBC channel. An MBC network protocol is implemented within the modem software. Some preliminary experiments were carried out for differential BPSK and differential QPSK modulations over a practical meteor burst link, and the results are presented.

In this paper, a new configuration method of multimode software radio system by parameter controlled and telecommunication component block embedded digital signal processing hardware (DSPH) is proposed for the future flexible multimedia communications. In this method, in advance, basic telecommunication component blocks are implemented in the DSPH like DSP and FPGA. And, external parameters, which are simple but important information, change the specification of each block. This proposed method has the following features: i) People need to have only one mobile handset and select communication services as they like. ii) The volume of download software is reduced drastically in comparison with conventional full-download-type software radio system. iii) Since important component blocks have already been implemented into the DSPH except for some external parameters in advance, the know-how related to the implementation of DSPH never leak out. In this paper, we evaluate the effectiveness of the proposed configuration method by using computer simulation and developed experimental prototype and comparing with full-download-type software radio system from the viewpoint of the volume of download software. Finally, we introduce several new software radio systems by using the proposed configuration method.

High-speed and low-power DSPs have been developed for versatile applications, especially for digital communications. These DSPs contain a 16-bit fixed point DSP core with multiple buses, highly tuned instruction set and low-power architecture, featuring 0.45 mA/MIPS, 100-120 MIPS performance by a single CPU core, 200 MIPS performance by dual CPU core architecture, respectively and also contain a 1.2 V low-voltage DSP core with 30 MIPS performance for super low-power applications. In this paper, new architecture VIA2 programming ROM for high-speed and new D flip-flop circuit considering the impact of pocket implantation process for low power are discussed, including key C-MOS process technology.

Multimedia mobile communication systems are expected to be realized in the near future. In such systems, multipath fading can cause severe degradations of the quality of the communications due to its wide bandwidth, especially in urban areas. Adaptive array antennas can be attractive solution for overcoming the multipath fading. Suppression can be achieved with the adaptive array by cophasing and combining multipath signals in the space and time domain. On the other hand, the concept of software antenna has been proposed. The software antenna recognizes radiowave environments and appropriately reconfigures itself for the signal processing required by the recognized environment. Efficient implementations can be expected if these functions are realized by the software. In this paper, we propose two types of the adaptive array systems which is reconfigurable depending on the radiowave environment as a realization of the concept of the software antenna. They recognize the environment by using the eigenvalue decomposition of space domain correlation matrices and reconfigure their structures of the signal processing. The principle and performance are examined by theoretical means and through computer simulations.

This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.

This paper presents a new binding algorithm for a retargetable compiler which can deal with diverse architectures of application specific embedded processors. The architectural diversity includes a "non-orthogonal" datapath configuration where all the registers are not equally accessible by all the functional units. Under this assumption, binding becomes a hard task because inadvertent assignment of an operation to a functional unit may rule out possible assignment of other operations due to unreachability among datapath resources. We propose a new BDD-based algorithm to solve this problem. While most of the conventional methods are based on the covering of expression trees obtained by decomposing DFGs, our algorithm works directly on the DFGs so as to avoid infeasible bindings. In the experiments, a feasible binding which satisfies the reachability is found or the deficiency of datapath is detected within a few seconds.

The development of saturation diving in civil and defense applications has enabled man to work in the sea at great depths and for long periods of time. This advance has resulted, in part, as a consequence of the substitution of helium for nitrogen in breathing gas mixtures. However, utilization of HeO2 breathing mixture at high ambient pressures has caused problems in speech communication; in turn, helium speech enhancement systems have been developed to improve diver communication. These speech unscramblers attempt to process variously the grossly unintelligible speech resulting from the effect of breathing mixtures and ambient pressure, and to reconstruct such signals in order to provide adequate voice communication. It is known that the glottal excitation is quasi-periodic and the vocal tract filter is quasi-stationary. Hence, it is possible to use an auto regressive modelisation to restore speech intelligibility in hyperbaric conditions. Corrections are made on the vocal tract transfer function, either in the frequency domain, or directly on the autocorrelation function. A spectral subtraction or noise reduction may be added to improve speech quality. A new VAD enhanced helium speech unscrambler is proposed for use in adverse conditions or in speech recognition. This system, implementable on single chip DSP of current technology, is capable to work in real time.

This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.

This paper presents the architecture of a newly-developed dual-issue RISC processor, D10V, that achieves both high throughput signal processing capability and maintains flexibility for general purpose applications. The RISC processor uses a 2-way VLIW architecture with a 32-bit wide instruction word. Two sub-instructions in a VLIW instruction are executed in two execution units in parallel. It also has several enhancements for signal processing. The processor includes pipelined multiply-and-accumulate instructions allowing a new multiply operation to be initiated every clock cycle and block repeat instructions for zero delay penalty loops. Single-cycle data moves of double-word data elements with modulo addressing are provided to deliver required memory bandwidth for signal processing applications. As a result, the D10V achieves high signal processing capability as 1 clock cycle per tap for FIR filtering. Also, several DSP benchmarks illustrate that the D10V competes favorably and in some instances outperforms conventional 16-bit DSPs. For master controlling application, the processor provides memory operations for signed/unsigned byte and bit wise operations. It shows 49 Dhrystone MIPS at 52 MHz, for general purpose applications.

A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.

A programmable DSP with linear array architecture for real-time video processing is reported. It achieves a processing rate of 5. 4 GOPS and 81GB/s memory bandwidth using Dual Sense Amplifier architecture. A low-power-supply pipeline decreases power consumption and a time shared bit-line reduces chip area. It has 4320 processor elements and a 1. 1 Mbit 3-port memory. The DSP can be applied to HDTV signals with its 75 MHz peak I/O rate. Sufficient programmability is provided to execute video format conversion such as image size conversion and Y/C separation, and picture quality improvement such as noise reduction and image enhancement. The chip was fabricated using 0. 4 µm CMOS triple metal technology with a 15. 12 mm 14. 95 mm die. It operates at 50 MHz and consumes 0. 53 W/GOPS at 3. 3 V.

Digital signal processors (DSPs) usually employ indirect addressing using an address register (AR) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. In this paper, AR update scheme is extended such that address can be efficiently modified by 2 in addition to conventional 1 updates. An automatic address allocation method of program variables for this new addressing model is presented. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained triangle graph, which is accessed only by AR 1 and 2 operations, so that the estimated number of overhead codes is minimized. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods.

We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beam-steering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

High level power estimation model is indispensable to optimize architecture and programs in terms of power consumption systematically. This paper describes power analysis results of a general purpose programmable DSP using switch level and cell based power simulation. The analysis results help to know characteristics of the DSP components and to establish a power estimation model. A compensation method for the lack of intra-cell capacitance in a cell based simulation is proposed to improve the simulation accuracy within -20% of error against the measured power. We considered that the error is caused by ignoring short circuit current and is accurate enough for this level of simulation. Through a result of the power breakdown by modules of the DSP obtained by the simulation, it was found that bus power is much less than generally expected (the simulated power is less than 5% of the total), and that the data operation power dominates the chip power (up to 33%) and is strongly data dependent. The reason that the bus power is low is because both of the load capacitance and the activity are low. Some correlation between the number of input signal transitions and the power consumption is found in each of an ALU, register file, and multiplier through further investigation on the data operation modules. The correlation is worthwhile to establish a power estimation model and is eventually useful to optimize a DSP architecture and DSP programs. The importance of power estimation model is demonstrated by showing an example in which we optimize an FIR filter program based upon the analysis results and proposed a direction of architecture optimization.

Asynchronous Transfer Mode (ATM) is considered to bo the key technology for realizing B-ISDN. This paper discusses current research on ATM switching nodes for high-speed communication networks. Although some ATM switching nodes have been deployed, much work continues for resolving problems as regards operations and maintainability, such as ATM layer performance evaluation including layered management scheme upon detection of line failure, function test methods regarding channel connectivity for multicasting, and real-time ATM traffic-monitoring mechanism with QoS control. To achieve sufficient ATM node maintainability, the ATM cell transfer quality on the VP and VC levels should be ensured both within the ATM nodes and between adjacent ATM nodes. Since ATM switching nods handle many kinds of virtual paths and virtual channels, each channel's connectivity must be confirmed. This paper proposes ATM layer performance evaluation concept, layered management scheme upon detection of line failure, function test methods for a multicast switch using test cells that periodically pass through pre-determined switching path routes. It also proposes the concept of test cell generation for simulating multiplexed ATM test cells taking ATM truffic characteristics into account. Furthermore, this paper describes a fault diagnosis scheme using test cells that can continually observe the entire ATM connection length in the system. A real-time traffic monitoring hardware configuration and an interface with software control are also discussed and it is clarified that the required functions can be realized by using commercially available DSPs.

In this paper, DSPs, of which memory addresses are pointed by special purpose registers (address registers: ARs), are assumed, and methods to derive an efficient memory access pattern for those DSPs proposed. In such DSPs, programmers must take care for efficient allocation of memory space as well as effective use of registers, in order to derive an efficient program in the sense of execution period. In this paper, memory addresses and AR update operations are modeled by an access graph, and a novel memory allocation method is presented. This method removes cycles and forks in a given access graph, and decides an address location of variables in memory space with less overhead. In order to utileze multiple ARs, methods to assign variables into ARs are investigated. The proposed methods are applied to the compiler for DSP56000 and are proved to be effective by generated codes for several examples.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.