The traditional manual inspection is gradually replaced by the unmanned aerial vehicles (UAV) automatic inspection. However, due to the limited computational resources carried by the UAV, the existing deep learning-based algorithm needs a large amount of computational resources, which makes it impossible to realize the online detection. Moreover, there is no effective online detection system at present. To realize the high-precision online detection of electrical equipment, this paper proposes an SSD (Single Shot Multibox Detector) detection algorithm based on the improved Dual network for the images of insulators and spacers taken by UAVs. The proposed algorithm uses MnasNet and MobileNetv3 to form the Dual network to extract multi-level features, which overcomes the shortcoming of single convolutional network-based backbone for feature extraction. Then the features extracted from the two networks are fused together to obtain the features with high-level semantic information. Finally, the proposed algorithm is tested on the public dataset of the insulator and spacer. The experimental results show that the proposed algorithm can detect insulators and spacers efficiently. Compared with other methods, the proposed algorithm has the advantages of smaller model size and higher accuracy. The object detection accuracy of the proposed method is up to 95.1%.

In this research, the effect of Ar/N2-plasma sputtering gas pressure on the LaBxNy tunnel and block layer was investigated for pentacene-based floating-gate memory with an amorphous rubrene (α-rubrene) passivation layer. The influence of α-rubrene passivation layer for memory characteristic was examined. The pentacene-based metal/insulator/metal/insulator/semiconductor (MIMIS) diode and organic field-effect transistor (OFET) were fabricated utilizing N-doped LaB6 metal layer and LaBxNy insulator with α-rubrene passivation layer at annealing temperature of 200°C. In the case of MIMIS diode, the leakage current density and the equivalent oxide thickness (EOT) were decreased from 1.2×10-2 A/cm2 to 1.1×10-7 A/cm2 and 3.5 nm to 3.1 nm, respectively, by decreasing the sputtering gas pressure from 0.47 Pa to 0.19 Pa. In the case of floating-gate type OFET with α-rubrene passivation layer, the larger memory window of 0.68 V was obtained with saturation mobility of 2.2×10-2 cm2/(V·s) and subthreshold swing of 199 mV/dec compared to the device without α-rubrene passivation layer.

We have investigated the in-situ N2-plasma nitridation for high-k HfN gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering to improve the electrical characteristics. It was found that the increase of nitridation gas pressure for the deposited HfN1.1 gate insulator, such as 98 mPa, decreased both the hysteresis width in C-V characteristics and leakage current. Furthermore, the 2-step nitiridation process with the nitridation gas pressure of 26 mPa followed by the nitridation at 98 mPa realized the decrease of equivalent oxide thickness (EOT) to 0.9 nm with decreasing the hysteresis width and leakage current. The fabricated metal-insulator-semiconductor field-effect transistor (MISFET) with 2-step nitridation showed a steep subthreshold swing of 87 mV/dec.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

In the past decade, real-time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

Silicon-on-insulator (SOI) has become one of the most famous materials in recent years, especially in silicon photonics applications. This paper presents a comparative performance of a SOI-based optical interconnect (OI) vs. an electrical interconnect (EI) for high-speed performances at a circuit level. The SOI-based optical waveguide was designed using OptiBPM to obtain a single mode condition (SMC). Then, the optical interconnect (OI) link was simulated in OptiSPICE and was tested as an interconnection in two-stage CS amplifiers. The results showed that the two-stage CS amplifier using OI offered several advantages in terms of electrical performances, such as voltage gain, frequency bandwidth, slew rate, and propagation delay, which makes it superior to the EI.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

In AlGaN/GaN high electron mobility transistors (HEMTs), drain current reduction by current collapse phenomenon is a big obstacle for a high efficient operation of power amplifier application. In this study, we investigated the effects of SiN passivation film quality on the electrical characteristics of AlGaN/GaN HEMTs. First, we conducted some experiments to investigate the relationship between electrical characteristics of AlGaN/GaN HEMTs and various conditions of SiN passivation film by plasma enhanced chemical vapor deposition (PE-CVD). We found that both gate current leakage and current collapse were improved simultaneously by SiN passivation film deposited by optimized condition of NH3 and SiH4 gas flow. It is found that the critical parameter in the optimization is a IN-H/ ISi-H ratio measured by Fourier transforms infrared spectroscopy (FT-IR) spectra. Next, a thermal CVD SiN was applied to the passivation film to be investigated from the same point of view, because a thermal CVD SiN is well known to have good quality with low hydrogen content and high IN-H/ISi-H ratio. We confirmed that the thermal CVD SiN passivation could improve much further both of the gate leakage current and the current collapse in AlGaN/GaN-HEMTs. Furthermore, we tried to apply the thermal CVD SiN to the gate insulator in MIS (Metal Insulator Semiconductor) structure of AlGaN/GaN HEMTs. The thermal CVD SiN passivation was more suitable for the gate insulator than PE-CVD SiN passivation in a view of reducing current collapse phenomena. It could be believed that the thermal CVD SiN film is superior to the PE-CVD SiN film to achieve good passivation and gate insulator film for AlGaN/GaN HEMTs due to the low hydrogen content and the high IN-H/ISi-H ratio.

We propose and demonstrate a simple one-bus two-ring configuration where the two rings are mutually coupled that has advantages over the one-ring structure. Unlike a one cavity system, it can exhibit near critically-coupled transmission with a broader range of loss. It can also significantly enhance the cavity finesse by simply making the second ring twice the size of the bus-coupled one, with the enhancement proportional to the intensity buildup in the second ring.

A model for the enhancement-mode operation of an AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MIS-HFET) under DC and AC conditions is proposed. In DC operation at positive gate voltages, the MIS-HFET can be divided into a transistor area and a resistor area due to the diode nature of the insulator/AlGaN interface. The transistor area shrinks with the increases in gate voltage. The intrinsic-transistor gate-length reduction causes a drain current increase. The I-V characteristics based on the gradual channel approximation are derived. The ID hysteresis of the MIS-HFET is investigated by a circuit simulation using SPICE. We have confirmed that the hysteresis was caused by the phase difference between the potential variation of the gate insulator/AlGaN interface and that of the gate electrode due to CR components in the gate structure.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

A multifunctional Boolean logic circuit composed of single-electron transistors (SETs) was fabricated and its operation demonstrated. The functions of Boolean logic can be changed by the half-period phase shift of the Coulomb-blockade (CB) oscillation of some SETs in the circuit, and an automatic control based on a feedback process is used to attain an exact shift. The amount of charges in the memory node (MN), which is capacitively coupled to the SET, controls the phase of the CB oscillation, and the output signal of the SET controls the amount of charge in the MN during the feedback process. This feedback process automatically adjusts SET output characteristics in such a way that it is used for the multifunctional Boolean logic. We experimentally demonstrated the automatic phase control and examined the speed of the feedback process by SPICE circuit simulation combined with a compact analytical SET model. The simulation revealed that programming time could be of the order of a few ten nanoseconds, thereby promising high-speed switching of the functions of the multifunctional Boolean logic circuit.

The driving frequency dependence of EL characteristics were investigated in thick ceramic insulating type thin-film electroluminescent (TFEL) devices with various Mn-activated Y2O3-based phosphor thin-film emitting layers driven by a sinusoidal wave voltage. High luminous efficiencies of approximately 10 and 1 lm/W were obtained in the TFEL devices driven at 60 Hz and 1 kHz, respectively. The difference in luminous efficiency was mainly caused by the increase of input power in 1 kHz-driven-devices resulting from a dielectric loss of a thick BaTiO3 ceramic sheet used as the insulating layer. The correlation between the sound emission from the devices and the effective power consumed in the devices was found with variations in both the applied voltage and the frequency. The higher input power of the 1 kHz-driven-device may be attributable to sound emissions resulting from the piezo-electricity of BaTiO3 ceramics.

A silicon (Si) wire waveguiding system fabricated on silicon-on-insulator (SOI) substrates is one of the most promising platforms for highly-integrated, ultra-small optical circuits, or microphotonics devices. The cross-section of the waveguide's core is about 300-nm-square, and the minimum bending radius are a few micrometers. Recently, crucial problems involving propagation losses and in coupling with external circuits have been resolved. Functional devices using silicon wire waveguides are now being tested. In this paper, we describe our recent progress and future prospects on the microphotonics devices based on the silicon-wire waveguiding system.

A new sputtering technique named "itshape limited reaction sputtering" is proposed and the feasibility toward an ultra-thin gate insulator is investigated. 5-10 nm thick ZrO2 films were prepared on Si(100) substrates and analyzed by XPS, HR-RBS and RHEED. Significant Zr diffusion into the Si substrate and interface oxidation were not observed. An optimum film was obtained at growth temperature of 300, oxygen flow rate of 4.2% and 500-10 sec RTA. The equivalent oxide thickness of 2 nm was realized with leakage current of 10-7 A/cm2 at 1.5 MV/cm.

The performance of radio frequency integrated circuits (RFICs) in silicon-on-insulator (SOI) technology can be improved by using a high-resistivity SOI substrate. We investigated the correlation between substrate resistivity and the performance of a low noise amplifier (LNA) on ELTRAN(R) SOI-Epi wafersTM, whose resistivity can be controlled precisely. The use of high-resistivity ELTRAN wafers improves the Q-factor of spiral inductors, and thereby increases the gain and narrows the bandwidth of the LNA. Using the high-resistivity ELTRAN wafers, we have successfully fabricated a 2.4-GHz and 5-GHz CMOS LNA in 0.35-µm SOI CMOS technology, whose process cost is lower than the latest CMOS technologies.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

We report, in this paper, on a combined process of photo-oxidation and PECVD using TEOS and O2 gases to produce an SiO2 gate insulator for poly-Si TFTs. Light of 172 nm-wavelength from a Xe excimer lamp generates active oxygen radicals efficiently and selectively without producing ozone. These oxygen radicals efficiently oxidize silicon. In contrast to plasma oxidation, photo-oxidation offers the ability to produce gate oxides without ion bombardment. Oxide-silicon interfaces with interface trap densities of 2-3 1010 cm-2 eV-1 were obtained by photo-oxidation at 200-300. A stack structure was produced using 4.3-nm-thick photo-oxide topped with a 40-nm-thick PECVD oxide film deposited at 300. This stack structure without annealing exhibited excellent interface behavior and the same J-E characteristics as a 100-nm-thick PECVD film annealed at 600.