We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

This letter presents the implementation framework of a video streaming server which uses an optical disk library as a source of media archiving. In order to handle the optical storage subsystem in the framework of disk-based stream service model, we have devised an effective stream scheduling, disk caching, and admission control mechanism. The proposed system has been implemented and its key principles are validated with real experiments.

A history of the English IEICE Transactions from the beginning is stated through the eyes of the person who has been involved in promoting the Transactions, by a description of why and how it has actually been reformed. The purpose and significance of the English IEICE Transactions, especially of the IEICE Trans. Fundamentals, are clarified.

Program slicing is a technique for statically analyzing a program and extracting an executable sub-program, which is called a program slice, from the original program. This technique has been widely applied to program testing, debugging and maintenance. This paper presents a slicing method for extracting program slices from a program that calls library functions, which are provided as object code. The method this paper presents analyzes dependence relationships between library functions using global data that are referred to by the library functions but not explicitly declared in a program. In this method, before slicing a program with respect to a slicing criterion, a Def-Slice-Use table will be generated that stores slice information for each function in the program by slicing these functions in advance, and then the program can be efficiently sliced using this table. The paper also illustrates some examples of program slicing using a program slicer LibSlicer that implements this method.

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.

As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.

In many applications of digital video database systems such as digital library, video data is often compressed with MPEG video algorithms. It will be an important technique to insert the additional information data like indexes and contents effectively into video database which is compressed with MPEG, because we can always deal with the additional information with video data itself easily. We propose a method for inserting optional binary data such as index information of digital library into MPEG-1 and -2 bitstreams. The binary data inserted MPEG video bitstreams using our proposed scheme are also according to the specification of the MPEG video frame structure. The proposed method allows us to extract the inserted binary data perfectly though MPEG-1 and -2 video are lossy algorithms. And the quality of decoded images after extracting added information is almost the same as that of ordinary MPEG bitstreams. Furthermore, traditional standard MPEG-1 and -2 video decoder which can not extract inserted binary data can also decode images from the binary data inserted MPEG video bitstreams without obvious image degradation. There are some different points between the proposed insertion technique of the binary data and the watermarking technique. The technique of watermarking prepares to deal with alter watermarking by others. And the technique of watermarking is required for the identification of the signature and the perfect extraction of the inserted image signature is not required in the lossy MPEG video environment. On the other hand, we have to extract all of the inserted binary information data correctly with the insertion technique of the binary information. Simulations using MPEG video sequences with inserted binary data are presented to quantify some performance factors concerned. We have not heard about inserting data method which purpose is such as index and content information insertion.