The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

There have been many developments on neural network research, and ability of a multi-layered network for classification of multi-spectral image data has been studied. We can classify non-Gaussian distributed data using the neural network trained by a back-propagation method (BPM) because it is independent of noise conditions. The BPM is a supervised classifier, so that we can get a high classification accuracy by using the method, so long as we can choose the good training data set. However, the multi-spectral data have many kinds of category information in a pixel because of its pixel resolution of the sensor. The data should be separated in many clusters even if they belong to a same class. Therefore, it is difficult to choose the good training data set which extract the characteristics of the class. Up to now, the researchers have chosen the training data set by random sampling from the input data. To overcome the problem, a hybrid pattern classification system using BPM and Kohonens feature mapping (KFM) has been proposed recently. The system performed choosing the training data set from the result of rough classification using KFM. However, how the remotely sensed data had been influenced by the KFM has not been demonstrated quantitatively. In this paper, we propose a new approach using the competitive weight vectors as the training data set, because we consider that a competitive unit represents a small cluster of the input patterns. The approach makes the training data set choice work easier than the usual one, because the KFM can automatically self-organize a topological relation among the target image patterns on a competitive plane. We demonstrate that the representative of the competitive units by principal component analysis (PCA). We also illustrate that the approach improves the classification accuracy by applying it on the classification of the real remotely sensed data.

Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.

In the program development process, it is ofren necessary for programmers to know the differences between two programs, or two different versions of a program. Since programs have structures such as iteration statement and selection statement, applying text-based tools such as UNIX diff to identify the differences may produce unsatisfactory results. In this paper, we exploit a tree as the internal representation of a program, obtain the mapping between two trees and display the program differences visually based on the mapping and pretty-printing technique so that the structural differences can be identified immediately.

This paper is concerned with synthesizing VLSI array processors from iterative algorithms. Our primary objective is to obtain the highest processor efficiency but not the shortest completion time. Unlike most of the previous work that assumes the index space of the given iterative algorithm to be boundless, the proposed method takes into account the effects of the boundaries of the index space. Due to this consideration, the pseudo-dependence relations are excluded, and most of the independent computations can therefore be uniformly grouped. With the method described in this paper, the index space is partitioned into equal-size blocks and the corresponding computations are systematically and uniformly mapped into processing elements. The synthesized VLSI array processors possess the attractive feature of very high processor efficiency, which, in general, is superior to what is derived from the conventional linear transformation methods.

Ever increasing demand for higher bandwidth memories, which is fueled by multimedia and 3D graphics, seems to be somewhat satisfied with various emerging memory solutions. This paper gives a review of these emerging DRAM architectures and a performance comparison based on a condition to let the readers have some perspectives of the future and optimized graphics systems.

We propose a stabilization method of unstable periodic orbits embedded in a chaotic attractor of continuous-time system by using discrete state feedback controller. The controller is designed systematically by the Poincar mapping and its derivatives. Although the output of the controller is applied periodically to system parameter as small perturbations discontinuously, the controlled orbit accomplishes C0. As the stability of a specific orbit is completely determined by the design of controller, we can also use the method to destabilize a stable periodic orbit. The destabilization method may be effectively applied to escape from a local minimum in various optimization problems. As an example of the stabilization and destabilization, some numerical results of Duffing's equation are illustrated.

The paper describes a new algorithm for Boolean matching, which is based on BDD structure manipulation. Pruning of the search space takes place after partial assignments if certain subgraphs of two BDD's become inequivalent. This pruning is different from existing techniques, so that the search space is further reduced. Another feature of this algorithm is topological filtering. Usually, many functions have no matchings and this is easily found by only counting the number of minterms. To check it quickly, upper and lower bounds of minterm count are calculated from topological information. Using these bounds, functions that have no matchings are discarded without building their BDD's.

In this paper, bifurcation and chaotic behavior which occur in simple looped MOS inverters with high speed operation are described. The most important point in this work is to change a nonlinear transfer characteristic of a MOS inverter to the nonlinearity generating a chaos. Three types of circuits which include four, three and one MOS inverters, respectively, are proposed. A switched capacitor (SC) circuit to operate sampling holding is added in the loop in each of the circuits. The bifurcation and chaotic behavior have been found along with a variation of an external input, and/or a sampling clock frequency. The bifurcation and chaotic behavior of the proposed simple looped MOS inverters are verified by employing SPICE circuit simulator as well as the experiments. For the first type of four looped CMOS inverters, Lyapunov exponent λ which has the positive regions for the chaotic behavior can be calculated by use of the fitting nonlinear function synthesized from two sigmoid functions. For the second type of three looped CMOS inverters and the third type of one looped MOS inverter, the nonlinear charge/discharge characteristics of the hold capacitor in the SC circuit is utilized efficiently for forming the nonlinearity generating the bifurcation and chaotic behavior. Their bifurcation can be generated by the sampling clock frequency parameter which is controlled easily.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

This paper describes a new method for pose estimation of human face moving abruptly in real world. The virtue of this method is to use a very simple calculation, disparity, among multiple model images, and not to use any facial features such as facial organs. In fact, since the disparity between input image and a model image increases monotonously in accordance with the change of facial pose, view direction, we can estimate pose of face in input image by calculating disparity among various model images of face. To overcome a weakness coming from the change of facial patterns due to facial individuality or expression, the first model image of face is detected by employing a qualitative feature model of frontal face. It contains statistical information about brightness, which are observed from a lot of facial images, and is used in model-based approach. These features are examined in everywhere of input image to calculate faceness" of the region, and a region which indicates the highest faceness" is taken as the initial model image of face. To obtain new model images for another pose of the face, some temporary model images are synthesized through texture mapping technique using a previous model image and a 3-D graphic model of face. When the pose is changed, the most appropriate region for a new model image is searched by calculating disparity using temporary model images. In this serial processes, the obtained model images are used not only as templates for tracking face in following image sequence, but also texture images for synthesizing new temporary model images. The acquired model images are accumulated in memory space and its permissible extent for rotation or scale change is evaluated. In the later of the paper, we show some experimental results about the robustness of the qualitative facial model used to detect frontal face and the pose estimation algorithm tested on a long sequence of real images including moving human face.

This paper proposes a methodology for fine evaluation of the uncertain behaviors of systems affected by any fluctuation of internal structures and internal parameters, by the use of a new concept on the fuzzy mapping. For a uniformly convex real Banach space X and Y, a fuzzy mapping G is introduced as the operator by which we can define a bounded closed compact fuzzy set G(x,y) for any (x,y)∈X×Y. An original system is represented by a completely continuous operator f defined on X, for instance, in a form xλ(f(x)) by a continuous operator λ: YX. The nondeterministic fluctuations induced into the original system are represented by a generalized form of the fuzzy mapping equation xGβ (x,f(x)) {ζX|µG(x,f(x))(ζ)β}, in order to give a fine evaluation of the solutions with respect to an arbitrarily–specified β–level. By establishing a useful fixed point theorem, the existence and evaluation problems of the "β–level-likely" solutions are discussed for this fuzzy mapping equaion. The theory developed here for the fluctuation problems is applied to the fine estimation of not only the uncertain behaviors of system–fluctuations but also the validity of system–models and -simulations with uncertain properties.

This paper reviews two topics of nonlinear system analysis done in Japan. The first half of this paper concerns with nonlinear system analysis through the nondeterministic operator theory. The nondeterministic operator is a set-valued or fuzzy set valued operator by K. Horiuchi. From 1975 Horiuchi has developed fixed point theorems for nondeterministic operators. Using such fixed point theorems, he developed a unique theory for nonlinear system analysis. Horiuchi's theory provides a fundamental view point for analysis of fluctuations in nonlinear systems. In this paper, it is pointed out that Horiuchi's theory can be viewed as an extension of the interval analysis. Next, Urabe's theory for nonlinear boundary value problems is discussed. From 1965 Urabe has developed a method of computer assisted existence proof for solutions of nonlinear boundary value problems. Urabe has presented a convergence theorem for a certain simplified Newton method. Urabe's theorem is essentially based on Banach's contraction mapping theorem. In this paper, reformulation of Urabe's theory using the interval analysis is presented. It is shown that sharp error estimation can be obtained by this reformulation. Both works discussed in this paper have been done independently with the interval analysis. This paper points out that they have deep relationship with the interval analysis. Moreover, it is also pointed out that these two works suggest future directions of the interval analysis.

The linear array processor architecture is an important class of interconnection structures that are suitable for VLSI. In this paper we study the problem of mapping a task tree onto a linear array to minimize the total execution time. First, an optimization algorithm is presented for a message scheduling probrem which occurs in the task tree mapping problem. Next, we give a heuristic algorithm for the task tree mapping problem. The algorithm partitions the node set of a task tree into clusters and maps these clusters onto processors. Simulation experiments showed that the proposed algorithm is much more efficient than a conventional algorithm.

This paper proposes an approach for approximately realizing nonlinear mappings of interval vectors by interval neural networks. Interval neural networks in this paper are characterized by interval weights and interval biases. This means that the weights and biases are given by intervals instead of real numbers. First, an architecture of interval neural networks is proposed for dealing with interval input vectors. Interval neural networks with the proposed architecture map interval input vectors to interval output vectors by interval arithmetic. Some characteristic features of the nonlinear mappings realized by the interval neural networks are described. Next, a learning algorithm is derived. In the derived learning algorithm, training data are the pairs of interval input vectors and interval target vectors. Last, using a numerical example, the proposed approach is illustrated and compared with other approaches based on the standard back-propagation neural networks with real number weights.

A new method for the DRAM soft-error evaluation was developed. By using a focused proton microprobe as a radiation source, and scanning it on a memory cell plane, local sensitive structure of memory cells against soft-errors could be investigated with a form of the susceptibility mapping. Cell mode and bit-line mode soft-errors could be clearly distinguished by controlling the incident location and the proton dose, and it was also found that the incident beam within 4 µm around the monitored memory cell caused the soft-error. The retrograde well formed by the MeV ion implantation technology was examined by this method. It was confirmed that the B+ layers in the retrograde well were a sufficient barrier against the charge collection. The generation rate of the electron-hole pairs and the charge collection into n+ layers with a retrograde well and a conventional well were estimated by the device simulator, and were explained the experimental results.

A hardware accelerator for a raster-based design-rule checking called BITDRC for a bit-mapping CAD system is described. BITDRC is a special-purpose hardware accelerator which performs design-rule checking for the Manhattan layout style VLSI circuis, much faster than the software checking which belonged to the bit-mapping CAD system before. The bit-mapping CAD system had effectively been developed for both of educational and VLSI design purposes, and just needs only a personal computer as a compact working environment. The proposed hardware architecture is rather simply and characterized by the bit-mapping CAD system where it works on. The hardware architecture and checking algorithm have been confirmed by implementing a bread-board prototype using discrete components. As a result, the processing time of BITDRC is speeded up as much as 500 times faster than the original software and takes only 4 seconds for checking every rule on a(15001500) grids layout pattern. BITDRC performs the error checking together with the data scanning that makes it can be as an on-line design-rule checker for the bit-mapping CAD system. Finally, the physical layout of BITDRC has been designed using a conventional CMOS technology.

In the direct product space of a complete metric linear space X and its related space Y, a fuzzy mapping G is introduced as an operator by which we can define a projective fuzzy set G(x,y) for any xX and yY. An original system is represented by a completely continuous operator f(x)Y, e.g., in the form x=λ(f(x)), (λ is a linear operator), and a nondeterministic or fuzzy fluctuation induced into the original system is represented by a generalized form of system equation xβG(x,f(x)). By establishing a new fixed point theorem for the fuzzy mapping G, the existence and evaluation problems of solution are discussed for this generalized equation. The analysis developed here for the fluctuation problem goes beyond the scope of the perturbation theory.