To elucidate the mechanism of topographic organization, we propose a simple topographic mapping formation model from generalized cell layer to generalized cell layer. Here generalized cell layer means that we consider arbitrary cell neighborhood relations. In our previous work we investigated a topographic mapping formation model between one dimensional cell layers. In this paper we extend the cell layer structure to any dimension. In our model, each cell takes a binary state value and we consider a class of learning principles which are extensions of Hebb's rule and Anti-Hebb's rule. We pay special attention to correlation type learning rules where a synaptic weight value is increased if pre and post synaptic cell states have the same value. We first show that a mapping is stable with respect to the correlational learning if and only if it is semi-embedding. Second, we introduce a special class of weight matrices called band type and show that the set of band type weight matrices is strongly closed and such a weight matrix can not yield a topographic mapping. Third, we show by computer simulations that a mapping, if it is defined by a non band type weight matrix, converges to a topographic mapping under the correlational learning rules.

Double Cross Cylinder (DCC) is an object created by intersecting the cylinder of Y-axis and the cylinder of the Z-axis. DCC mapping is a new method for effectively mapping the environment. This method eliminates the singularity effect caused in the environment maps and shows an almost even amount of area for the environment occupied by a single texel. The surrounding environment can also be stored more effectively through more accurate sampling. Improvement is also achieved in the rendering time of the DCC mapping method and octahedral mapping method based on DCC mapping. Therefore, the DCC mapping method is suitable to be applied on environment navigation systems due to its effective storage of the environment and faster sampling time.

A generic multilevel quality-of-service (QoS) model for distributed multimedia applications is presented. QoS mapping mechanisms are required to translate the QoS parameters among the hierarchical levels. One QoS mapping mechanism based on the spline functions is proposed, hence two splines are compared. One is natural splines and the other is B-splines. QoS measurement experiments were conducted, and it is found that the B-splines give more accurate mapping results than the natural splines once the knots for the splines are selected appropriately.

This paper proposes a method for mapping a finite state machine (FSM) into a two-dimensional array of LUTs, which is a part of our plastic cell architecture (PCA). LSIs based on the PCA have already implemented as asynchronous devices. Functions that run on the LSIs must also be asynchronous. In order to make good use of the LSIs, a system that translates functions into circuit information for the PCA is needed. We introduce a prototype system that maps an asynchronous FSM onto the PCA. First, a basic mapping method is considered, and then we create three methods to minimize circuit size. Some benchmark suites are synthesized to estimate their efficiency. Experimental results show that all the methods can map an asynchronous FSM onto the PCA and that the three methods can effectively reduce circuit size.

Footprint assembly was proposed to reduce the blurriness of texture mapped image by mipmapping. Even though it can improve the quality of texture mapped image, there are yet blurring due to the limitation of it's filter kernel. This paper proposes a novel texture filtering, called adaptive footprint assembly (AFA), to overcome the limitation of footprint assembly. The proposed method greatly improves the quality of texture mapped images.

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

A method to reduce the bandwidth between texture memory and the rasterization processor is proposed. It achieves the reduction by not fetching useless texels from texture memory in bilinear filtering. Since it does not depend on cache and loss compression, it can be used in applications where the reusability of texels is low and loss compression is prevented.

In this paper, we shall construct mathematical theory based on the concept of set-valued mappings, suitable for available operation of network systems extraordinarily complicated and diversified on large scales. Fundamental conditions for availability of system behaviors of such network systems are clarified in a form of fixed point theorem for system of set-valued mappings.

This work presents a novel description of texture mapping polygons in a geometric view about scanlines and a simplified mapping function to improve the performance. The conventional perspective-correct mapping requires costly division operations. In this work, two concepts in perspective geometry, cross-ratio and vanishing point, are exploited to simplify the mapping function. We substitute the point at infinity on scanline into the cross-ratio equation, then obtain a simple description of perspective mapping in polygons. Our mapping function allows the spatial mapping of a pixel from a scanline on a screen plane to a texture plane taking only one division, one multiplication and three additions. The proposed algorithm speeds up the mapping process without losing any correctness. Experimental results indicate that the performance of proposed method is superior to other correct mapping methods.

This paper proposes a synchronous acquisition method using correlation mapping by multiple-dwell detection considering false alarm penalty in M-ary/SS systems. In the method, first, the correlation value between a received signal and each assigned sequence in an M-ary/SS system in some short duration is calculated for each phase and stored in the mapping. Second, the maximum correlation value of each phase in the mapping is selected and arranged, then, the first probable synchronous phase is decided by the maximum one in these values. Simultaneously, data demodulation starts. Next, to recognize the synchronous phase, i.e., as considering false alarm penalty, the correlation values are calculated in longer duration, and the second probable phase with high reliability can be obtained by suppression of noise to signal level. Finally, if the second synchronous phase is different from the first one, the second one is reset. By this method, a short acquisition time and high reliability of acquisition can be achieved. The improvement of acquisition time and the optimal combination values of dwelling time, which is duration to calculate the correlation, are shown for several conditions in asynchronous M-ary/SSMA.

In any ill-conditioned information-transfer system, as in long-distance communication, we often must construct feedback confirmation channels, in order to confirm that informations received at destinations are correct. Unfortunately, for such systems, undesirable uncertain fluctuations may be induced not only into forward communication channels but also into feedback confirmation channels, and it is such difficult that transmitters always confirm correct communications. In this paper, two fuzzy-set-valued mappings are introduced into both the forward communication channel and the feedback confirmation channel, separately, and overall system-behaviors are discussed from the standpoint of functional analysis, by means of fixed point theorem for a system of generalized equations on fuzzy-set-valued mappings. As a result, a good mathematical condition is successfully obtained, for such information-transfer systems, and fine-textured estimations of solutions are obtained, at arbitrary levels of values of membership functions.

Loss analysis in bent graded-index optical slab waveguides is given using the modal-matching method. The conformal mapping replaces curved structure by an equivalent straight waveguide with a modified index profile. For this planar waveguide structure, the normal modes are calculated using a multilayer approximation method. The wave incident on the bend is expanded initially into a finite set of normal modes of the equivalent straight structure, and the transverse fields are matched across the junction. The numerical results show the loss formation in the graded-index waveguides and its dependence of the effective index of the corresponding straight waveguide.

A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.

Recently, Plastic Cell Architecture (PCA) has been proposed as a hard-wired general-purpose autonomously reconfigurable processor. PCA consists of two layers, the plastic part on which sequential logic circuits are implemented, and the built-in part which induces the plastic part to dynamically reconfigure the circuits and transports messages among the circuits. The plastic part consists of an array of LUT-based reconfigurable logic primitives, each of which is connected only to adjacent ones. Combining logic and layout synthesis, we propose a new array-based algorithm to map logic functions into the PCA plastic part. This algorithm produces a folded array of sum-of-multi-input-complex-terms, especially for the PCA plastic part.

This paper proposes an associative memory neural network whose limiting state is the nearest point in a polyhedron from a given input. Two implementations of the proposed associative memory network are presented based on Dykstra's algorithm and a fixed point theorem for nonexpansive mappings. By these implementations, the set of all correctable errors by the network is characterized as a dual cone of the polyhedron at each pattern to be memorized, which leads to a simple amplifying technique to improve the error correction capability. It is shown by numerical examples that the proposed associative memory realizes much better error correction performance than the conventional one based on POCS at the expense of the increase of necessary number of iterations in the recalling stage.

This paper proposes an automatic method for reconstructing a realistic 3D facial image from CT (computer tomography) and three color photographs: front, left and right views, which can be linked easily with the underlying bone and soft tissue models. This work is the first part of our final goal, "the prediction of patient's facial appearance after cancer surgery" such as removal of a part of bone or soft tissues. The 3D facial surface derived from CT by the marching cubes algorithm is obviously colorless. Our task is to add the color texture of the same patient actually taken with a digital camera to the colorless 3D surface. To do this it needs an accurate registration between the 3D facial image and the color photograph. Our approach is to set up a virtual camera around the 3D facial surface to register the virtual camera images with the corresponding color photographs by automatically adjusting seven parameters of the virtual camera. The camera parameters consists of three rotations, three translations and one scale factor. The registration algorithm has been developed based upon Besl and McKay's iterative closest point (ICP) algorithm.

In multi-media systems, the type of interactive communication channels is found almost everywhere and plays an important role, as well as the type of unilateral communication channels. In this report, we shall construct a fluctuation theory based on the concept of set-valued mappings, suitable for evaluation, control and operation of interactive communication channels in multi-media systems, complicated and diversified on large scales. Fundamental conditions for availability of such channels are clarified in a form of fixed point theorem for system of set-valued mappings.

This paper presents a technique for miniaturization of microstrip line and coplanar waveguide for microwave integrated circuits by using airbridge technology. A theoretical analysis is given by a combination of the conformal mapping technique and the variational principle. Numerical results demonstrate significant effects on size reduction as well as wide range of the characteristic impedance variation due to the airbridge.

This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.